EPM9320LI84-20N vs EPM9320ALC84-20 비교
다음의 상세 나란히 비교: EPM9320LI84-20N 제조: Altera 및 EPM9320ALC84-20 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM9320LI84-20N | EPM9320ALC84-20 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $10.50 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 to 12,000 | — |
| User I/O Pins | 60 | — |
| Total Pins | 84 | — |
| 패키지 | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | PLCC-84 |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | — |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) | — |
| Maximum Counter Frequency | 118 MHz | — |
| Logic Family | CMOS, EEPROM-based | — |
| 공급 전압 | 5.0 V | 5.0 V |
| 동작 온도 | 0 C to +70 C (commercial) | [DATA_NEEDED: commercial or industrial grade] |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| Process Technology | Advanced CMOS EEPROM | 0.5 µm CMOS EEPROM |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: per Altera datasheet] |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/Os | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| 실장 유형 | — | Surface Mount (PLCC socket compatible) |
| Configuration Memory | — | Non-volatile EEPROM |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Design Software | — | MAX+PLUS II / Quartus II (legacy) |