EPM9320LI84-20N vs EPM9320ALI84-10 Comparison
Detailed side-by-side comparison of EPM9320LI84-20N by Altera and EPM9320ALI84-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320LI84-20N | EPM9320ALI84-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $19.95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 to 12,000 | 6,000 to 12,000 |
| User I/O Pins | 60 | 84 |
| Total Pins | 84 | β |
| Package | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | β |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) | β |
| Maximum Counter Frequency | 118 MHz | 144 MHz |
| Logic Family | CMOS, EEPROM-based | β |
| Supply Voltage | 5.0 V | β |
| Operating Temperature | 0 C to +70 C (commercial) | β |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable | β |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array MatriX (MAX) |
| Process Technology | Advanced CMOS EEPROM | CMOS |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | β |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Pin-to-Pin Delay (Tpd1) | β | 10 ns |
| Supply Voltage (VCC) | β | 5.0 V |
| In-System Programmability | β | Yes, via IEEE 1149.1 JTAG |
| Program Memory Technology | β | CMOS EEPROM |
| Operating Temperature Range | β | -40C to +85C (Industrial) |
| Mounting Type | β | Surface Mount (PLCC socket compatible) |