EPM9320RC208-10 vs EPM9320ARC208-10N Comparison
Detailed side-by-side comparison of EPM9320RC208-10 by Altera and EPM9320ARC208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9320RC208-10
EPM9320RC208-10 - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320RC208-10 NrndAltera
EPM9320ARC208-10N
EPM9320ARC208-10N - 320-Macrocell MAX 9000 CPLD, 10ns | Altera
EPM9320ARC208-10N ObsoleteSpecification Comparison
| Parameter | EPM9320RC208-10 | EPM9320ARC208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $26.40 | $19.45 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | β |
| Macrocells | 320 | β |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | 16 |
| Package | 208-pin RQFP (RC) | 208-pin RQFP (BFQFP with exposed pad) |
| Operating Temperature | Commercial (0C to +70C) - 'C' suffix | 0C to +70C (Commercial) |
| Supply Voltage | 5 V | β |
| Speed Grade | -10 | β |
| Programming Interface | JTAG (ByteBlaster/BitBlaster) | IEEE Std. 1149.1 JTAG |
| Non-volatile Configuration | Yes (EPROM/EEPROM based) | β |
| Design Tool Support | MAX+PLUS II, Quartus (legacy) | β |
| RoHS Status | ROHS3 Compliant (per fpgalink listing) | Compliant (lead-free 'N' suffix) |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) | β |
| Lead Time | 1-7 days (per fpgalink listing) | β |
| Macro Cells | β | 320 |
| Logic Gates | β | 6,000 gates |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Frequency | β | 144.9 MHz |
| Supply Voltage (VCC) | β | 5 V |
| User I/O Pins | β | 168 |
| Dedicated Input Pins | β | 12 |
| Mounting Type | β | Surface Mount |
| Configuration Memory | β | Non-volatile EEPROM |