EPM9320RC208-15 vs EPM9320RC208-10 Comparison
Detailed side-by-side comparison of EPM9320RC208-15 by Altera and EPM9320RC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320RC208-15 | EPM9320RC208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Device Family | MAX 9000 | — |
| Macro Cells | 320 | — |
| Usable Gates | 6,000 | 6,000 |
| Pin-to-Pin Propagation Delay | 15 ns (speed grade -15) | — |
| Maximum Clock Frequency | 117.6 MHz | — |
| Supply Voltage | 5.0 V | 5 V |
| Configuration Technology | EEPROM-based (non-volatile) | — |
| In-System Programmability | Yes (ISP via JTAG) | — |
| JTAG Interface | IEEE Std. 1149.1 | — |
| Package | 208-pin RQFP (Power QFP) | 208-pin RQFP (RC) |
| Package Type | 208-BFQFP Exposed Pad | — |
| Mounting Type | Surface Mount | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) - 'C' suffix |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Logic Array Blocks | [DATA_NEEDED: LAB count] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | ROHS3 Compliant (per fpgalink listing) |
| Lifecycle Status | Obsolete (PDN0706, 2007) | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 320 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Speed Grade | — | -10 |
| Programming Interface | — | JTAG (ByteBlaster/BitBlaster) |
| Non-volatile Configuration | — | Yes (EPROM/EEPROM based) |
| Design Tool Support | — | MAX+PLUS II, Quartus (legacy) |
| Moisture Sensitivity Level (MSL) | — | 3 (168 Hours) |
| Lead Time | — | 1-7 days (per fpgalink listing) |