EPM9320RC208-15 vs EPM9320RC208-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320RC208-15 sa pamamagitan ng Altera at EPM9320RC208-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320RC208-15 | EPM9320RC208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Family | MAX 9000 | — |
| Macro Cells | 320 | — |
| Usable Gates | 6,000 | 6,000 |
| Pin-to-Pin Propagation Delay | 15 ns (speed grade -15) | — |
| Maksimum na Taktiko ng Oras | 117.6 MHz | — |
| Volte ng Pagbibigay | 5.0 V | 5 V |
| Configuration Technology | EEPROM-based (non-volatile) | — |
| In-System Programmability | Yes (ISP via JTAG) | — |
| JTAG Interface | IEEE Std. 1149.1 | — |
| Packhaging | 208-pin RQFP (Power QFP) | 208-pin RQFP (RC) |
| Package Type | 208-BFQFP Exposed Pad | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) - 'C' suffix |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Logic Array Blocks | [DATA_NEEDED: LAB count] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | ROHS3 Compliant (per fpgalink listing) |
| Katayuan ng Lifecycle | Obsolete (PDN0706, 2007) | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 320 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Speed Grade | — | -10 |
| Programming Interface | — | JTAG (ByteBlaster/BitBlaster) |
| Non-volatile Configuration | — | Yes (EPROM/EEPROM based) |
| Design Tool Support | — | MAX+PLUS II, Quartus (legacy) |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | 3 (168 Hours) |
| Lead Time | — | 1-7 days (per fpgalink listing) |