EPM9320RC208-15 vs EPM9320RC208-20 Comparison
Detailed side-by-side comparison of EPM9320RC208-15 by Altera and EPM9320RC208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320RC208-15 | EPM9320RC208-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $21.90 |
| Device Family | MAX 9000 | β |
| Macro Cells | 320 | β |
| Usable Gates | 6,000 | 6,000 |
| Pin-to-Pin Propagation Delay | 15 ns (speed grade -15) | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Supply Voltage | 5.0 V | β |
| Configuration Technology | EEPROM-based (non-volatile) | β |
| In-System Programmability | Yes (ISP via JTAG) | β |
| JTAG Interface | IEEE Std. 1149.1 | β |
| Package | 208-pin RQFP (Power QFP) | 208-RQFP, exposed pad (208-BFQFP) |
| Package Type | 208-BFQFP Exposed Pad | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0 Β°C to 70 Β°C (commercial) |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | β |
| Logic Array Blocks | [DATA_NEEDED: LAB count] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Lifecycle Status | Obsolete (PDN0706, 2007) | β |
| Family | β | MAX 9000 |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 320 |
| Logic Array Blocks (LABs) | β | 20 |
| Maximum I/O Pins | β | 132 |
| Propagation Delay (tPD max) | β | 20 ns |
| Supply Voltage (VCCINT) | β | 4.75 V to 5.25 V |
| Programming Technology | β | EEPROM, in-system programmable (ISP) |
| Boundary-Scan Interface | β | IEEE Std. 1149.1 (JTAG) |
| Architecture | β | Multiple Array Matrix (MAX), 3rd generation |
| Process Technology | β | CMOS, 5.0 V EEPROM |
| Reprogrammability | β | Yes, unlimited ISP cycles |