EPM9320RI208-20 vs EPM9320RC208-20 Comparison

Detailed side-by-side comparison of EPM9320RI208-20 by Intel and EPM9320RC208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320RI208-20 EPM9320RC208-20
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 320 320
Usable Gates 6,000 6,000
Propagation Delay (tPD) 20 ns —
Maximum Operating Frequency 100 MHz —
Supply Voltage (VCC) 5.0 V —
Logic Elements / LABs 20 Logic Array Blocks (16 macro cells each) —
Programmable Interconnect Programmable Interconnect Array (PIA) —
In-System Programmability Yes - IEEE 1149.1 JTAG, 5.0-V ISP —
Dedicated Input Pins 4 (low-skew global) —
User I/O Pins [DATA_NEEDED: I/O pin count for 208-pin RQFP] —
Package 208-pin RQFP (Power Quad Flat Pack) 208-RQFP, exposed pad (208-BFQFP)
Operating Temperature Grade Industrial —
Technology CMOS EEPROM —
Mounting Type Surface Mount Surface Mount
MSL Level [DATA_NEEDED: MSL rating] —
RoHS Status [DATA_NEEDED: RoHS compliance] —
Logic Array Blocks (LABs) — 20
Maximum I/O Pins — 132
Propagation Delay (tPD max) — 20 ns
Supply Voltage (VCCINT) — 4.75 V to 5.25 V
Programming Technology — EEPROM, in-system programmable (ISP)
Boundary-Scan Interface — IEEE Std. 1149.1 (JTAG)
Operating Temperature — 0 °C to 70 °C (commercial)
Architecture — Multiple Array Matrix (MAX), 3rd generation
Process Technology — CMOS, 5.0 V EEPROM
Reprogrammability — Yes, unlimited ISP cycles

Datasheets & Resources

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