EPM9320RI208-20 - MAX 9000 CPLD, 320 Macrocells, 20ns | Intel
MPN: EPM9320RI208-20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $27.2 | $2,720.00 |
| 500 | $22.4 | $11,200.00 |
| 1,000 | $18.95 | $18,950.00 |
Drop-in alternatives for EPM9320RI208-20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9320RI208-10N
β Drop-Inβ In Stock
$27.2 / Unit
View Datasheet βEPM9320RI208-15
β Drop-Inπ Reference alternative (not in catalog)
EPM9320RC208-20
β Drop-Inβ In Stock
$21.9 / Unit
View Datasheet βEPM9320RC208-20N
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPM9320RC208-15N
β Drop-Inβ In Stock
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View Datasheet βEPM9320RC208-15
β Drop-Inβ In Stock
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View Datasheet βEPM9320RC208-10
β Drop-Inβ In Stock
$26.4 / Unit
View Datasheet βEPM9320RI208-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 |
| Usable Gates | 6,000 |
| Propagation Delay (tPD) | 20 ns |
| Maximum Operating Frequency | 100 MHz |
| Supply Voltage (VCC) | 5.0 V |
| Logic Elements / LABs | 20 Logic Array Blocks (16 macro cells each) |
| Programmable Interconnect | Programmable Interconnect Array (PIA) |
| In-System Programmability | Yes - IEEE 1149.1 JTAG, 5.0-V ISP |
| Dedicated Input Pins | 4 (low-skew global) |
| Package | 208-pin RQFP (Power Quad Flat Pack) |
| Operating Temperature Grade | Industrial |
| Technology | CMOS EEPROM |
| Mounting Type | Surface Mount |
EPM9320RI208-20 Pin Configuration
| Pin 1 | I/O β User I/O pin (signal direction programmable) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | GCLK1 β Dedicated global clock input 1 (low-skew) |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | OE1 β Dedicated global output enable input 1 |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | CLR1 β Dedicated global clear input 1 |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | VCC β 5.0-V supply voltage |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | GCLK2 β Dedicated global clock input 2 (low-skew) |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | OE2 β Dedicated global output enable input 2 |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | TDI β JTAG Test Data In |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | TMS β JTAG Test Mode Select |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | TCK β JTAG Test Clock |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | VCC β 5.0-V supply voltage |
| Pin 41 | TDO β JTAG Test Data Out |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | CLR2 β Dedicated global clear input 2 |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | VCC β 5.0-V supply voltage |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | GND β Ground |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | VCC β 5.0-V supply voltage |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | GND β Ground |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
| Pin 85 | I/O β User I/O pin |
| Pin 86 | VCC β 5.0-V supply voltage |
| Pin 87 | I/O β User I/O pin |
| Pin 88 | I/O β User I/O pin |
| Pin 89 | I/O β User I/O pin |
| Pin 90 | I/O β User I/O pin |
| Pin 91 | I/O β User I/O pin |
| Pin 92 | I/O β User I/O pin |
| Pin 93 | GND β Ground |
| Pin 94 | I/O β User I/O pin |
| Pin 95 | I/O β User I/O pin |
| Pin 96 | I/O β User I/O pin |
| Pin 97 | I/O β User I/O pin |
| Pin 98 | I/O β User I/O pin |
| Pin 99 | I/O β User I/O pin |
| Pin 100 | VCC β 5.0-V supply voltage |
| Pin 101 | I/O β User I/O pin |
| Pin 102 | I/O β User I/O pin |
| Pin 103 | I/O β User I/O pin |
| Pin 104 | I/O β User I/O pin |
| Pin 105 | I/O β User I/O pin |
| Pin 106 | I/O β User I/O pin |
| Pin 107 | GND β Ground |
| Pin 108 | I/O β User I/O pin |
| Pin 109 | I/O β User I/O pin |
| Pin 110 | I/O β User I/O pin |
| Pin 111 | I/O β User I/O pin |
| Pin 112 | I/O β User I/O pin |
| Pin 113 | I/O β User I/O pin |
| Pin 114 | VCC β 5.0-V supply voltage |
| Pin 115 | I/O β User I/O pin |
| Pin 116 | I/O β User I/O pin |
| Pin 117 | I/O β User I/O pin |
| Pin 118 | I/O β User I/O pin |
| Pin 119 | I/O β User I/O pin |
| Pin 120 | I/O β User I/O pin |
| Pin 121 | GND β Ground |
| Pin 122 | I/O β User I/O pin |
| Pin 123 | I/O β User I/O pin |
| Pin 124 | I/O β User I/O pin |
| Pin 125 | I/O β User I/O pin |
| Pin 126 | I/O β User I/O pin |
| Pin 127 | I/O β User I/O pin |
| Pin 128 | VCC β 5.0-V supply voltage |
| Pin 129 | I/O β User I/O pin |
| Pin 130 | I/O β User I/O pin |
| Pin 131 | I/O β User I/O pin |
| Pin 132 | I/O β User I/O pin |
| Pin 133 | I/O β User I/O pin |
| Pin 134 | I/O β User I/O pin |
| Pin 135 | GND β Ground |
| Pin 136 | I/O β User I/O pin |
| Pin 137 | I/O β User I/O pin |
| Pin 138 | I/O β User I/O pin |
| Pin 139 | I/O β User I/O pin |
| Pin 140 | I/O β User I/O pin |
| Pin 141 | I/O β User I/O pin |
| Pin 142 | VCC β 5.0-V supply voltage |
| Pin 143 | I/O β User I/O pin |
| Pin 144 | I/O β User I/O pin |
| Pin 145 | I/O β User I/O pin |
| Pin 146 | I/O β User I/O pin |
| Pin 147 | I/O β User I/O pin |
| Pin 148 | I/O β User I/O pin |
| Pin 149 | GND β Ground |
| Pin 150 | I/O β User I/O pin |
| Pin 151 | I/O β User I/O pin |
| Pin 152 | I/O β User I/O pin |
| Pin 153 | I/O β User I/O pin |
| Pin 154 | I/O β User I/O pin |
| Pin 155 | I/O β User I/O pin |
| Pin 156 | VCC β 5.0-V supply voltage |
| Pin 157 | I/O β User I/O pin |
| Pin 158 | I/O β User I/O pin |
| Pin 159 | I/O β User I/O pin |
| Pin 160 | I/O β User I/O pin |
| Pin 161 | I/O β User I/O pin |
| Pin 162 | I/O β User I/O pin |
| Pin 163 | GND β Ground |
| Pin 164 | I/O β User I/O pin |
| Pin 165 | I/O β User I/O pin |
| Pin 166 | I/O β User I/O pin |
| Pin 167 | I/O β User I/O pin |
| Pin 168 | I/O β User I/O pin |
| Pin 169 | I/O β User I/O pin |
| Pin 170 | VCC β 5.0-V supply voltage |
| Pin 171 | I/O β User I/O pin |
| Pin 172 | I/O β User I/O pin |
| Pin 173 | I/O β User I/O pin |
| Pin 174 | I/O β User I/O pin |
| Pin 175 | I/O β User I/O pin |
| Pin 176 | I/O β User I/O pin |
| Pin 177 | GND β Ground |
| Pin 178 | I/O β User I/O pin |
| Pin 179 | I/O β User I/O pin |
| Pin 180 | I/O β User I/O pin |
| Pin 181 | I/O β User I/O pin |
| Pin 182 | I/O β User I/O pin |
| Pin 183 | I/O β User I/O pin |
| Pin 184 | VCC β 5.0-V supply voltage |
| Pin 185 | I/O β User I/O pin |
| Pin 186 | I/O β User I/O pin |
| Pin 187 | I/O β User I/O pin |
| Pin 188 | I/O β User I/O pin |
| Pin 189 | I/O β User I/O pin |
| Pin 190 | I/O β User I/O pin |
| Pin 191 | GND β Ground |
| Pin 192 | I/O β User I/O pin |
| Pin 193 | I/O β User I/O pin |
| Pin 194 | I/O β User I/O pin |
| Pin 195 | I/O β User I/O pin |
| Pin 196 | I/O β User I/O pin |
| Pin 197 | I/O β User I/O pin |
| Pin 198 | VCC β 5.0-V supply voltage |
| Pin 199 | I/O β User I/O pin |
| Pin 200 | I/O β User I/O pin |
| Pin 201 | I/O β User I/O pin |
| Pin 202 | I/O β User I/O pin |
| Pin 203 | I/O β User I/O pin |
| Pin 204 | I/O β User I/O pin |
| Pin 205 | GND β Ground |
| Pin 206 | I/O β User I/O pin |
| Pin 207 | I/O β User I/O pin |
| Pin 208 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320RI208-20 is suitable for 6 applications: Industrial Automation Controllers, Glue Logic and Address Decoding, Telecommunications Bus Bridges, State Machine Implementation, Embedded System Peripheral Expansion, Legacy System Modernization and Form-Fit Replacements.
Industrial Automation Controllers
The EPM9320RI208-20 is well-suited for industrial automation controllers because its 320 macro cells and 6,000 usable gates provide enough logic density for complex state machines, encoder/decoder logic, and PLC-style ladder replacement, while its industrial temperature grade and 5-V supply tolerance match factory-floor environments. The 100 MHz maximum operating frequency and 20 ns tPD allow deterministic timing for real-time control loops, and the EEPROM-based non-volatile configuration eliminates boot-time delays critical to machine startup. The 4 dedicated low-skew global input pins can distribute high-speed encoder signals across the chip without timing skew. Designers can implement glue logic between microcontrollers, sensor front-ends, and motor drivers on a single device.
Recommended
Glue Logic and Address Decoding
The EPM9320RI208-20 excels as a glue-logic integration device for microprocessor systems where address decoding, chip-select generation, and wait-state insertion must be deterministic and instantly available at power-up. Its 320 macro cells and Programmable Interconnect Array (PIA) provide predictable timing regardless of routing, while the EEPROM configuration guarantees instant-on behavior without an external boot PROM. The 5-V VCC and TTL-compatible I/O allow direct connection to legacy 80C186, 68k, and 8051-family microprocessors without level translation. The device's 20 ns tPD comfortably decodes memory cycles in systems running up to 25 MHz, and the 208-pin RQFP package provides ample I/O for 16- and 32-bit bus implementations.
Recommended
Telecommunications Bus Bridges
The EPM9320RI208-20 is frequently deployed in telecommunications equipment as a bus-bridge between legacy and modern interfaces, because its 320 macro cells and 6,000 usable gates can implement protocol converters (e.g., PCI-to-ISA, UART multiplexing, HDLC framing) on a single chip. The 5.0-V supply and TTL-compatible I/O simplify integration into legacy telecom linecards, while the IEEE 1149.1 JTAG interface allows in-field firmware updates as standards evolve. The 100 MHz maximum internal frequency supports common telecom clock domains, and the device's deterministic 20 ns tPD is ideal for synchronous bus turnaround. Industrial temperature operation is critical for outdoor or uncontrolled-environment installations.
Recommended
State Machine Implementation
The EPM9320RI208-20 is ideally suited for complex state-machine controllers in embedded systems because its MAX 9000 macrocell architecture is designed around D-flip-flops with programmable output enables, making it straightforward to implement Moore and Mealy machines with 50+ states. The 20 LABs each provide 16 macro cells with shared local feedback, allowing efficient one-hot and binary state encoding without wasting logic. The deterministic 20 ns tPD and 100 MHz internal frequency ensure that even worst-case state transitions complete within budget. EEPROM configuration makes the device instantly ready at power-on, critical for safety interlocks and machine-tool controllers.
Recommended
Embedded System Peripheral Expansion
The EPM9320RI208-20 is often used to expand the I/O capabilities of microcontrollers and embedded processors that lack sufficient native GPIO or peripheral interfaces. Its 208-pin RQFP package exposes a large number of user I/O pins that can be configured individually as input, output, or bidirectional, with TTL/CMOS-compatible thresholds directly matching 5-V microcontrollers. The 320 macro cells can implement PWM generators, quadrature decoders, SPI/I2C master/slave controllers, and UART channels on a single chip. The deterministic timing allows accurate PWM generation for motor control, and the JTAG ISP allows firmware updates without dismantling the end product.
Recommended
Legacy System Modernization and Form-Fit Replacements
The EPM9320RI208-20 is widely used in legacy system modernization, particularly for industrial controls, medical devices, and aerospace systems built in the 1990s and 2000s, where the original Altera MAX 9000 design must be reproduced on a one-for-one basis. Its identical 208-pin RQFP footprint, JTAG-based ISP, and EEPROM configuration ensure that existing PCBs and design files can be supported without modification. Engineers can also migrate firmware from -20 speed grade to -15 or -10 speed grades without PCB changes, gaining timing margin while preserving the proven design. Industrial temperature grade and 5-V tolerance match the supply environment of legacy equipment.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320RI208-20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320RI208-10N | EPM9320RI208-15 | EPM9320RC208-20 | EPM9320RC208-20N | EPM9320RC208-15N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Propagation Delay (tPD) | 20 ns | 10 ns | 15 ns | 20 ns | 20 ns | 15 ns |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 |
| Usable Gates | 6,000 | 6,000 | 6,000 | 6,000 | 6,000 | 6,000 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | Industrial | Industrial | Industrial | Commercial | Commercial | Commercial |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Lead-Free (N suffix) | No | Yes (N suffix) | No | No | Yes (N suffix) | Yes (N suffix) |
Key Differentiators
- Industry-standard 5-V CPLD with EEPROM non-volatile configuration (vs EPM9320RI208-10N)
- Industrial temperature grade vs commercial grade (vs EPM9320RC208-20)
- Largest MAX 9000 device in 208-pin RQFP (vs EPM7256SQC208-10)
Design Notes
The EPM9320RI208-20 operates from a single 5.0-V VCC supply and the datasheet requires that VCC rise monotonically during power-up to ensure proper EEPROM configuration load. Place decoupling capacitors (0.1 uF ceramic in parallel with 10 uF tantalum or low-ESR electrolytic) as close as possible to every VCC pin on the package to minimize supply noise. There are typically 11 VCC and 11 GND pins distributed around the 208-pin RQFP perimeter for optimal power distribution. Estimated: typical VCCIO current consumption for the EPM9320 family is 100-300 mA depending on toggle rate and output loading, so the regulator should be sized with at least 30% headroom.
The 208-pin RQFP package requires careful PCB layout because of its high pin count (0.5 mm pitch) and gull-wing leads. Use 4-layer PCB stack-up with continuous power and ground planes; route signal traces on inner layers for controlled impedance where needed. The four dedicated global input pins (GCLK1, GCLK2, OE1/OE2, CLR1/CLR2) should be routed with matched trace lengths to minimize clock skew across the device. Estimated: the exposed thermal pad is not present on RQFP packages, so thermal management relies on copper pour around the perimeter.
JTAG boundary-scan integrity is essential for in-system programming of the EPM9320RI208-20. Ensure TDI, TMS, TCK, and TDO traces are kept short and free of stubs; add 10 kohm pull-ups on TDI, TMS, and TCK to prevent floating state during power-up. The minimum DC input voltage on user I/O pins is -0.5 V (and -0.3 V on dedicated inputs) - inputs may undershoot to -2.0 V for periods shorter than 20 ns under no-load conditions, but this must not be exceeded. Place series termination resistors on long JTAG chains to suppress ringing.
A common pitfall when designing with the EPM9320RI208-20 is assuming sufficient macro cells remain after synthesis - the design must fit within 320 macro cells and the available PIA routing. Always run a Quartus or MAX+PLUS II fitter report to confirm 100% utilization is achievable; pin-to-pin tPD of 20 ns only holds when the design is fully routed. The -20 speed grade is the slowest in the MAX 9320 family; do not use it for designs requiring >25 MHz register-to-register timing. Use the EPM9320RI208-10 (10 ns tPD) instead for high-frequency state machines or high-speed bus bridges.
Compliance Information
Lead-free status depends on -N suffix variant. The base EPM9320RI208-20 is non-N (with lead). RoHS and REACH compliance not explicitly stated in the verified web data - mark as unknown per data authenticity rules.
