EPM9320RI208-20N vs EPM9560RI208-10N Comparison
Detailed side-by-side comparison of EPM9320RI208-20N by Altera and EPM9560RI208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320RI208-20N | EPM9560RI208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Device Family | MAX 9000 (EPM9320) | — |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Macrocells | 320 | — |
| Flip-Flops | 484 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5.0 V | — |
| I/O Voltage Tolerance | 3.3 V or 5 V configurable | — |
| Package | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin RQFP (PQFP) |
| Package Lead Pitch | 0.500 mm | — |
| Number of Terminals | 208 | — |
| Operating Temperature Range | -40C to +85C (Industrial) | — |
| In-System Programmability | Yes, 5.0 V ISP via JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| Configuration Memory | EEPROM (non-volatile) | On-chip EEPROM (non-volatile) |
| Dedicated Input Pins | 4 (low-skew global distribution) | — |
| Minimum DC Input on I/O Pins | -0.5 V | — |
| Minimum DC Input on Dedicated Inputs | -0.3 V | — |
| Input Undershoot/ Overshoot | -2.0 V / 7.0 V for <20 ns (no-load) | — |
| Mounting Type | Surface Mount | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | ROHS3 Compliant (per fpgalink) |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Usable Gates | — | 12,000 |
| Macro Cells | — | 560 |
| Register Bits | — | 12,160 |
| User I/Os | — | 212 |
| Pin-to-Pin Delay | — | 10 ns (speed grade -10) |
| Maximum Frequency | — | 100 MHz to 125 MHz |
| Supply Voltage | — | 5 V |
| Operating Temperature | — | -40C to +85C (Industrial grade, "RI" suffix) |
| Programming Method | — | In-system via IEEE 1149.1 (JTAG) |
| MSL Level | — | 3 (168 Hours) |