EPM9480RC208-15N vs EPM9560RI208-15N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9480RC208-15N disebabkan oleh Altera dan EPM9560RI208-15N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM9480RC208-15N | EPM9560RI208-15N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 10,000 | — |
| Macro Cells | 480 | — |
| Maximum Frequency | 117.6 MHz | — |
| Propagation Delay | 15 ns (speed grade -15) | — |
| Tegangan Pemberi Arus | 5.0 V | 5.0 V |
| Kemasan | 208-pin RQFP | 208-pin RQFP (Ruggedized Quad Flat Pack) |
| Jenis Pemasangan | Surface Mount | — |
| Configuration Memory | EEPROM (non-volatile) | CMOS EEPROM, in-system programmable |
| In-System Programmability | Yes (ISP via JTAG) | — |
| JTAG Interface | IEEE Std. 1149.1 | — |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | 0C to 70C (Commercial) |
| Status RoHS | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level | MSL 3 (168 Hours) | — |
| Manufacturer Standard Lead Time | 1-7 Days | — |
| Architecture | Multiple Array MatriX (MAX) third-generation | Multiple Array MatriX (MAX), 3rd generation |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Device Family | — | MAX 9000 |
| Total Pins | — | 356 (per third-party catalog; see _validation_note) |
| Package Pin Count | — | 208 |
| Terminal Form | — | Gull Wing |
| Package Code | — | HFQFP |
| User I/Os | — | 216 (per DigiChip specification; see _validation_note) |
| Maximum Internal Frequency | — | 145 MHz |
| Propagation Delay (tPD) | — | 11.4 ns (15 ns speed grade) |
| Speed Grade | — | -15 |
| Temperature Grade | — | Industrial (per Vyrian/Partstack listings) |
| Logic Family | — | CMOS |
| Programming Interface | — | IEEE 1149.1 JTAG, 5.0-V in-system |