EPM9560ARC240-10N vs EPM9560RC-10 Comparison
Detailed side-by-side comparison of EPM9560ARC240-10N by Altera and EPM9560RC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560ARC240-10N - MAX 9000 CPLD 560 Macro 191 IOs | Altera/Intel
EPM9560ARC240-10N ObsoleteSpecification Comparison
| Parameter | EPM9560ARC240-10N | EPM9560RC-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Logic Family | MAX 9000 (CPLD) | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Macro Cells | 560 | — |
| User I/Os | 191 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Frequency (fMAX) | 145 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Operating Temperature | 0°C to +70°C (Commercial) | 0C to +70C (commercial) |
| Package | 240-pin RQFP (32x32 mm) | 240-pin PGA (RC suffix) |
| Mounting Type | Surface Mount | Through-Hole / Socketed |
| Programming Interface | IEEE 1149.1 JTAG / ByteBlaster | — |
| Programmability | In-system, EEPROM-based (non-volatile) | — |
| I/O Standard | 5.0 V TTL-compatible | — |
| RoHS Status | Non-RoHS (legacy Altera part) | unknown |
| Family | MAX 9000 | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 560 |
| Usable Gates | — | 12,000 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| In-System Programmability | — | IEEE 1149.1 JTAG |
| Architecture | — | Multiple Array Matrix (MAX) - third generation |