EPM9560ARC240-10N - MAX 9000 CPLD 560 Macro 191 IOs | Altera/Intel
MPN: EPM9560ARC240-10N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $27.2 | $2,720.00 |
| 500 | $22.9 | $11,450.00 |
| 1,000 | $19.5 | $19,500.00 |
Drop-in alternatives for EPM9560ARC240-10N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560ARC240-10
✅ Drop-In✓ In Stock
$28.8 / Unit
View Datasheet →EPM9560RC240-15
✅ Drop-In📋 Reference alternative (not in catalog)
EPM9560ARC240-10N Maximum Ratings & Electrical Characteristics
| Logic Family | MAX 9000 (CPLD) |
| Process Technology | CMOS EEPROM |
| Macro Cells | 560 |
| User I/Os | 191 |
| Logic Array Blocks (LABs) | 16 |
| Propagation Delay (tPD) | 10 ns |
| Internal Frequency (fMAX) | 145 MHz |
| Supply Voltage (VCCINT) | 5.0 V |
| Operating Temperature | 0°C to +70°C (Commercial) |
| Package | 240-pin RQFP (32x32 mm) |
| Mounting Type | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG / ByteBlaster |
| Programmability | In-system, EEPROM-based (non-volatile) |
| I/O Standard | 5.0 V TTL-compatible |
| RoHS Status | Non-RoHS (legacy Altera part) |
| Family | MAX 9000 |
EPM9560ARC240-10N Pin Configuration
| Pin 1 | I/O — General-purpose user I/O (bank 1) |
| Pin 60 | GND — Ground |
| Pin 120 | VCC — 5.0 V core supply |
| Pin 180 | I/O — General-purpose user I/O (bank 2) |
| Pin 240 | I/O — General-purpose user I/O (bank 2) |
| Pin JTAG | TCK/TMS/TDI/TDO — IEEE 1149.1 JTAG pins - refer to MAX 9000 device handbook for exact pin numbers |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560ARC240-10N is suitable for 6 applications: 5V Telecom Backplane Glue Logic, ISA/PCI Bus Address Decoding and Interrupt Control, Microprocessor to DSP Peripheral Bridge, Industrial Control State Machine, Legacy Peripheral Replacement for 74-series TTL, JTAG-Based In-System Programming Hub.
5V Telecom Backplane Glue Logic
The EPM9560ARC240-10N is well suited to 5V telecom backplane glue logic because its 191 user I/Os and 560 macrocells provide enough logic capacity to integrate wide address decoders, chip-select generators, and bus-arbiter state machines in a single non-volatile CPLD. Its 10 ns pin-to-pin propagation delay and 145 MHz internal frequency match typical TDM bus and H.110 backplane timing margins at 8 MHz / 16 MHz. Unlike an FPGA, the device boots in microseconds from its on-chip EEPROM, eliminating external boot PROM complexity on hot-swap telecom cards. Designers typically place the CPLD between a microprocessor and a switch fabric ASIC, using JTAG for in-field firmware updates.
Recommended
ISA/PCI Bus Address Decoding and Interrupt Control
The EPM9560ARC240-10N's 560 macrocells and 191 I/Os make it a strong fit for legacy ISA and PCI bus address decoders, interrupt controllers, and bus-bridge glue logic in industrial single-board computers. Each macrocell provides a dedicated product-term array with predictable tPD, which is critical for PCI bus arbitration cycles that require decoding within a fixed number of clocks. The 5V-tolerant I/Os interface directly to legacy ISA bus transceivers without external level shifters. Designers use the JTAG chain to load custom address maps per board variant, replacing dozens of 74-series TTL decoder chips with one non-volatile CPLD.
Recommended
Microprocessor to DSP Peripheral Bridge
In embedded designs that pair a PowerPC, ARM, or MIPS host with a DSP coprocessor, the EPM9560ARC240-10N acts as a peripheral bridge that converts host bus cycles to DSP HPI or McBSP interfaces while generating chip selects and DMA handshakes. The 191 I/Os comfortably accommodate 32-bit data plus 24-bit address plus control signals, leaving headroom for status LEDs and JTAG. With 10 ns tPD the CPLD meets typical 66 MHz host-bus timing without wait states. EEPROM-based configuration means the bridge is operational before the host finishes its boot ROM, simplifying cold-start sequencing.
Recommended
Industrial Control State Machine
The EPM9560ARC240-10N is widely used in industrial PLC and motor-control boards as the deterministic state machine that sequences power-converter switching, fault detection, and safety interlocks. MAX 9000's deterministic 10 ns tPD regardless of routing complexity removes the timing uncertainty that complicates FPGA-based state machines in safety-critical loops. With 191 I/Os the device can simultaneously drive IGBT gate drivers, sample analog comparator outputs, and communicate over CAN or RS-485. The 0 to +70°C commercial grade is adequate for enclosed industrial cabinets with proper thermal management.
Recommended
Legacy Peripheral Replacement for 74-series TTL
Designers use the EPM9560ARC240-10N to consolidate dozens of 74LS, 74F, and 74AS decoder, multiplexer, and register chips into a single non-volatile CPLD on legacy 5V boards. The 560 macrocells typically replace 30 to 60 equivalent TTL packages, freeing board area and reducing power consumption while preserving the 5V interface levels expected by surrounding ICs. The 10 ns tPD matches the speed of 74F and 74AS logic, so timing margins are preserved without redesign. JTAG-based in-system programming allows last-minute logic changes during board bring-up without re-spinning the BOM.
Recommended
JTAG-Based In-System Programming Hub
The EPM9560ARC240-10N's dedicated JTAG port (TDI/TDO/TMS/TCK) and 191 general-purpose I/Os make it an effective JTAG programming hub or boundary-scan controller on multi-chip boards. Designers route the CPLD's JTAG chain to downstream microcontrollers, DSPs, and flash memories, and use spare macrocells to generate TRST, reset, and programming-voltage sequencing signals. The EEPROM-based MAX 9000 architecture boots in microseconds, so the JTAG hub is available before the main processor begins initialization. This simplifies factory test fixtures and field firmware updates for legacy 5V systems.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560ARC240-10N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560ARC240-10 | EPM9560RC240-15 | EPM9560ARC208-10N |
|---|---|---|---|---|
| Brand | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) |
| Package | 240-pin RQFP (32x32 mm) | 240-pin RQFP - same | 240-pin RQFP - same | 208-pin RQFP - smaller |
| Macro Cells | 560 | 560 | 560 | 560 |
| User I/Os | 191 | 191 | 191 | 159 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 15 ns (slower, -33%) | 10 ns |
| Internal Frequency (fMAX) | 145 MHz | 145 MHz | 125 MHz | 145 MHz |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Lead-Free Finish | Yes (N suffix) | No (SnPb) | [DATA_NEEDED] | Yes (N suffix) |
| Lifecycle Status (as of 2026-09-13) | Obsolete / End-of-life planned | Obsolete / End-of-life planned | Obsolete / End-of-life planned | Obsolete / End-of-life planned |
Key Differentiators
- Highest macrocell density in 240-RQFP MAX 9000 family (vs EPM9320ARC208-10N)
- Lead-free (RoHS) terminal finish (vs EPM9560ARC240-10)
- Fastest speed grade in the MAX 9560 family (vs EPM9560RC240-15)
Design Notes
Estimated: at VCC = 5.0 V and typical ICC of 250 mA with all 191 I/Os toggling, the EPM9560ARC240-10N dissipates approximately 1.25 W. Place a 10 µF tantalum bulk capacitor and a 0.1 µF ceramic decoupling capacitor within 5 mm of each VCC/GND pin pair (the 240-RQFP has multiple VCC and GND pins distributed around the package). Add a ferrite bead on the 5V supply rail if the board shares the rail with switching converters, as MAX 9000 I/O switching transients can inject noise into adjacent analog sections.
The 240-pin RQFP package has a typical θJA of approximately 30 °C/W. Estimated: at 1.25 W dissipation the junction-to-ambient rise is about 37 °C, so junction temperature stays below 110 °C even at +70 °C ambient, well within the commercial 0 to +70 °C spec. No external heatsink is required, but ensure at least 4 square inches of inner-plane copper are stitched to GND beneath the package to spread heat and provide a low-impedance return path for switching I/O currents.
Route all 5 V supply traces at least 0.5 mm wide with a ground return directly beneath, and keep high-speed clock outputs (fOUT > 50 MHz) shorter than 25 mm to limit radiated emissions. Place the JTAG chain header within 50 mm of the TDI/TDO pins to minimize stub reflections; add a 10 kΩ pull-up on TCK and TMS per IEEE 1149.1. For multi-board JTAG chains, include jumpers to bypass the CPLD during board-level test of downstream devices.
Do not confuse the EPM9560ARC240-10N with the EPM9560ATC144-10 (144-pin TQFP, fewer I/Os) - they are not drop-in compatible. Ensure the ByteBlaster or JTAG programmer voltage matches the I/O bank voltage; mixing 3.3 V programmers with 5 V CPLD I/Os can damage the device. Always program with the latest MAX+PLUS II or Quartus MAX 9000 support files; older software may not recognize the -10N RoHS variant. Finally, verify the silicon revision against the MAX 9000 errata sheet before committing the design to production.
Maintain a continuous ground plane on the layer directly beneath the CPLD; this provides controlled impedance for high-speed I/O and reduces EMI. Use 45° bends (no right angles) on clock and high-speed I/O traces longer than 10 mm. Keep parallel traces between layers orthogonal to minimize crosstalk. If the design uses the global FastTrack interconnect at high frequency, reserve at least 8 mm of clearance around the JTAG pins to allow in-system programming probe access during board bring-up.
Compliance Information
EPM9560ARC240-10N has lead-free terminal finish (N suffix) but the underlying silicon and package materials contain antimony/other substances that may affect RoHS exemption status under category 7 (industrial monitoring). Not AEC-Q100 qualified - commercial grade 0 to +70°C only. Reach compliance per Altera/Intel product declaration.
