EPM9560ARI240-10N vs EPM9560GC280-15 Comparison
Detailed side-by-side comparison of EPM9560ARI240-10N by Intel and EPM9560GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560ARI240-10N - MAX 9000 CPLD, 560 Macrocells, 5V, 240-RQFP | Intel
EPM9560ARI240-10N NrndAltera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteSpecification Comparison
| Parameter | EPM9560ARI240-10N | EPM9560GC280-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 | — |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 16 | — |
| User I/Os | 216 (per digchip); 191 (per Mouser) | — |
| Maximum Internal Frequency | 144.9 MHz (typical); 145 MHz (per digchip) | — |
| Propagation Delay (tPD) | 10 ns (-10 speed grade) | — |
| Supply Voltage | 5.0 V nominal (4.5 V min, 5.5 V max) | — |
| Logic Family | CMOS, EEPROM-based | — |
| In-System Programmability | Yes (5.0 V ISP via JTAG) | — |
| Package | 240-pin RQFP (RQFP-240 / PQFP-240) | — |
| Mounting Type | Surface Mount | Through-Hole |
| Operating Temperature | -40C to +85C (industrial) | — |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation | Multiple Array MatriX (MAX) |
| JTAG (IEEE 1149.1) | Yes | — |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free / RoHS status not in provided data] | — |
| Device Type | — | EE PLD (CMOS EEPROM-based CPLD) |
| Macro Cells | — | 560 |
| Typical Gates | — | 12,000 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | — | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Package Type | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Programmability | — | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Technology | — | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| RoHS Status | — | Non-compliant (ceramic CPGA, contains lead) |
| Lifecycle Status | — | Obsolete (legacy Altera MAX 9000 family) |