EPM9560GC280-20N - 560 Macrocell MAX 9000 CPLD, 280-Pin CPGA | Altera
MPN: EPM9560GC280-20N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $418 | $418.00 |
| 10 | $380 | $3,800.00 |
| 100 | $345 | $34,500.00 |
| 500 | $310 | $155,000.00 |
| 1,000 | $285 | $285,000.00 |
Drop-in alternatives for EPM9560GC280-20N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560GC280-20
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View Datasheet →EPM9560GC280-15N
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View Datasheet →EPM9560GC280-15
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View Datasheet →EPM9560ELI84-20
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View Datasheet →EPM9560GC280-20N Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation |
| Technology | CMOS EEPROM-based |
| Usable Gates | 6,000 to 12,000 |
| Macrocells | 560 |
| User I/O Pins | 212 |
| Pin-to-Pin Delay (tPD) | 20 ns |
| Maximum Counter Frequency | 144 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| I/O Voltage | 3.3 V or 5 V (configurable) |
| In-System Programmability | Yes (5.0-V ISP via IEEE 1149.1 JTAG) |
| Package | 280-pin CPGA (Ceramic Pin Grid Array) |
| Configuration Memory | EEPROM (non-volatile, instant-on) |
| PCI Compliance | Yes |
EPM9560GC280-20N 280-pin cpga (ceramic pin grid array) Pin Configuration Guide
Complete pinout information for EPM9560GC280-20N (280-pin cpga (ceramic pin grid array) package) with 212 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560GC280-20N.
Refer to the datasheet for full pin configuration.
Estimated pin count: 212 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560GC280-20N is suitable for 6 applications: PCI Bus Interface Logic, High-Speed Processor-to-Peripheral Glue Logic, DSP and Microcontroller Address Decoding, Legacy Industrial Control Replacement, JTAG Boundary-Scan Test Infrastructure, Bus Arbitration and DMA Control.
PCI Bus Interface Logic
The EPM9560GC280-20N's 212 user I/O pins and PCI compliance make it well-suited for bridging processor buses to 33 MHz / 66 MHz PCI peripherals. With a 20 ns tPD and 144 MHz counter frequency, the device meets PCI 2.2 timing budgets for address decoding, command/byte-enable decoding, and target/initiator state machines. Place the CPLD between the host CPU and PCI bus to consolidate glue logic, decode CONFIG address space, and arbitrate IRQ lines — eliminating discrete 74-series logic and shrinking board area. Verified Web Data confirms the MAX 9000 family is officially PCI-compliant.
Recommended
High-Speed Processor-to-Peripheral Glue Logic
The EPM9560GC280-20N's 560 macrocells and 20 ns tPD deliver deterministic combinational logic for processor-to-memory and processor-to-peripheral glue functions. The EEPROM-based MAX architecture provides instant-on behavior at power-up, eliminating boot-PROM delay for address decoding, chip-select generation, and wait-state insertion. Compared to discrete TTL/CMOS glue, the integrated CPLD reduces board real-estate, improves noise immunity, and is fully reprogrammable via the on-chip IEEE 1149.1 JTAG interface — enabling field upgrades without replacing the device.
Recommended
DSP and Microcontroller Address Decoding
The 212 I/O pins of the EPM9560GC280-20N allow full address-bus decoding for memory-mapped peripherals in DSP and 32-bit microcontroller systems. Each macrocell contains a programmable AND/OR array with a configurable flip-flop supporting D, T, JK, and SR modes, enabling complex state-machine decode logic with predictable 20 ns tPD. Use it to decode chip-selects for external SRAM, Flash, and peripherals while offloading address-decode logic from the main CPU — improving system throughput and simplifying PCB routing.
Recommended
Legacy Industrial Control Replacement
The EPM9560GC280-20N's 5.0-V core operation and 4.75-5.25 V supply tolerance make it ideal for replacing obsolete 74-series and PAL-based control logic in industrial automation systems where 5 V rails remain standard. With EEPROM non-volatile storage, the device retains its configuration through power cycles without external boot devices, supporting long-life factory-floor installations. The 280-pin CPGA ceramic package suits legacy through-hole industrial designs and conformal-coated assemblies where surface-mount CPLDs may be unsuitable.
Recommended
JTAG Boundary-Scan Test Infrastructure
The EPM9560GC280-20N's built-in IEEE Std. 1149.1 JTAG interface allows it to serve as a JTAG chain master or slave in board-level boundary-scan test infrastructure. Use it to chain together multiple JTAG devices for in-system programming and bed-of-nails test access. The 144 MHz counter frequency and predictable timing support high-speed boundary-scan clocking, and the 5.0-V ISP feature enables field firmware updates via the same JTAG port used for production testing — minimizing field-service cost.
Recommended
Bus Arbitration and DMA Control
The EPM9560GC280-20N's combination of 560 macrocells and 212 I/O pins supports multi-master bus arbitration, DMA handshake logic, and interrupt-priority encoding in shared-bus architectures. Each macrocell's flip-flop operates up to 144 MHz, enabling sub-microsecond arbitration latency for high-throughput systems. Use it to implement round-robin or priority-based arbiters, hand-off FIFOs, and request/grant state machines in backplane designs, multiprocessor systems, or RAID storage controllers — replacing multiple discrete PALs and latches.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560GC280-20N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560GC280-20 | EPM9560GC280-15N | EPM9560GC280-15 | EPM9560ELI84-20 |
|---|---|---|---|---|---|
| Package | 280-pin CPGA | 280-pin CPGA - same | 280-pin CPGA - same | 280-pin CPGA - same | 84-pin PLCC - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 560 | 560 | 560 | 560 | [DATA_NEEDED] |
| Pin-to-Pin Delay (tPD) | 20 ns | 20 ns | 15 ns (-25%) | 15 ns (-25%) | 20 ns |
| User I/O Pins | 212 | 212 | 212 | 212 | [DATA_NEEDED] |
| Usable Gates | 6,000 to 12,000 | 6,000 to 12,000 | 6,000 to 12,000 | 6,000 to 12,000 | [DATA_NEEDED] |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | [DATA_NEEDED] |
| Maximum Counter Frequency | 144 MHz | 144 MHz | 144 MHz | 144 MHz | [DATA_NEEDED] |
Key Differentiators
- Pin-to-pin upgrade path to 15 ns speed grade (vs EPM9560GC280-15N)
- Non-volatile EEPROM configuration eliminates boot PROM (vs SRAM-based FPGA alternatives)
- 5.0-V ISP via built-in JTAG (vs Modern MAX II/MAX V CPLDs (3.3 V core))
Design Notes
The EPM9560GC280-20N operates from a single 4.75 V to 5.25 V supply. Per Altera MAX 9000 guidelines, place one 0.1 µF decoupling capacitor per VCC/GND pin pair on the 280-pin CPGA, plus a single 10 µF bulk tantalum capacitor near the device supply pin. ICC rises with output switching frequency — at full 144 MHz counter operation with 50% I/O toggle, expect peak transient currents of several hundred mA. Add bulk capacitance at the board entry point.
For the 280-pin CPGA ceramic package, use a socket or plated-through-hole footprint designed for PGA pin geometry (1.27 mm typical). Maintain continuous ground and power planes on adjacent inner layers for the high-pin-count BGA-style escape routing. JTAG signals (TCK, TMS, TDI, TDO) should be series-terminated with 33 Ω resistors if chain length exceeds 100 mm. Keep the JTAG port accessible at the board edge for ISP programming via the on-chip IEEE 1149.1 interface.
Do not confuse the EPM9560GC280-20N with the EPM9320GC280-20 (320 macrocells, lower density) — same package, different die. Verify the exact Altera ordering code on the top marking before substituting. The 'N' suffix may indicate industrial temperature or lead-free finish per Altera ordering information; consult the datasheet for the specific grade of your part. For legacy designs, confirm supply voltage (5 V) and I/O voltage (3.3 V vs 5 V) match the system before PCB integration.
The 212 user I/O pins of the EPM9560GC280-20N operate at PCI-compliant edge rates. For high-speed outputs above 50 MHz, use series damping resistors (22-33 Ω) to suppress ringing on long PCB traces. Configure I/O standards (3.3 V or 5 V) per the Altera Quartus pin-assignment file before compilation — mixing standards on the same bank can damage the device. The IEEE 1149.1 JTAG pins must remain stable during normal operation; do not use JTAG pins as general-purpose I/O.
Compliance Information
RoHS, REACH, and lead-free status are not stated in the verified web data. The 'N' suffix on the part number may denote a lead-free finish — verify against the manufacturer datasheet ordering information. NRND (Not Recommended for New Designs) per Octopart distributor listing (2026-09-13).
