EPM9560GC280-20N vs EPM9560GI280-20 Comparison
Detailed side-by-side comparison of EPM9560GC280-20N by Altera and EPM9560GI280-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560GC280-20N | EPM9560GI280-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $285.00 | $162.50 |
| Family | MAX 9000 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Technology | CMOS EEPROM-based | β |
| Usable Gates | 6,000 to 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| User I/O Pins | 212 | β |
| Pin-to-Pin Delay (tPD) | 20 ns | β |
| Maximum Counter Frequency | 144 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5.0 V |
| I/O Voltage | 3.3 V or 5 V (configurable) | β |
| In-System Programmability | Yes (5.0-V ISP via IEEE 1149.1 JTAG) | Yes (IEEE Std. 1149.1 JTAG) |
| Package | 280-pin CPGA (Ceramic Pin Grid Array) | 280-pin PGA (PIN/PEG, square) |
| Configuration Memory | EEPROM (non-volatile, instant-on) | β |
| PCI Compliance | Yes | β |
| Operating Temperature | [DATA_NEEDED: industrial/commercial grade] | β |
| RoHS Status | [DATA_NEEDED] | [DATA_NEEDED: RoHS status for GI PGA package] |
| Device Family | β | MAX 9000 |
| Technology Node | β | 5.0 V CMOS EEPROM |
| Logic Array Blocks (LABs) | β | 28 (16 macrocells each) |
| Maximum User I/O Pins | β | 216 |
| Flip-Flops | β | 772 |
| Pin-to-Pin Delay (Speed Grade) | β | 20 ns |
| Programming Technology | β | EEPROM (non-volatile) |
| Terminal Form | β | PIN/PEG (through-hole PGA) |
| Package Code | β | PGA |
| Temperature Grade | β | Industrial |
| I/O Pin DC Input Range | β | -0.5 V to VCC + 0.5 V |
| Dedicated-Input Pin DC Input Range | β | -0.3 V to VCC + 0.3 V |
| I/O Transient Envelope (no-load, <20 ns) | β | -2.0 V undershoot to 7.0 V overshoot |
| VCC Ramp Requirement | β | Monotonic rise |
| Development Tool | β | Altera MAX+PLUS II |
| Supported HDLs | β | VHDL, Verilog HDL, AHDL |