EPM9560GC280-20N vs EPM9560GI280-20 比較
詳細並排比較 EPM9560GC280-20N 由 Altera 與 EPM9560GI280-20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560GC280-20N | EPM9560GI280-20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Technology | CMOS EEPROM-based | — |
| Usable Gates | 6,000 to 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| User I/O Pins | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5.0 V |
| I/O Voltage | 3.3 V or 5 V (configurable) | — |
| In-System Programmability | Yes (5.0-V ISP via IEEE 1149.1 JTAG) | Yes (IEEE Std. 1149.1 JTAG) |
| 封裝 | 280-pin CPGA (Ceramic Pin Grid Array) | 280-pin PGA (PIN/PEG, square) |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| PCI Compliance | Yes | — |
| 工作溫度 | [DATA_NEEDED: industrial/commercial grade] | — |
| RoHS 狀態 | [DATA_NEEDED] | [DATA_NEEDED: RoHS status for GI PGA package] |
| Device Family | — | MAX 9000 |
| Technology Node | — | 5.0 V CMOS EEPROM |
| Logic Array Blocks (LABs) | — | 28 (16 macrocells each) |
| Maximum User I/O Pins | — | 216 |
| Flip-Flops | — | 772 |
| Pin-to-Pin Delay (Speed Grade) | — | 20 ns |
| Programming Technology | — | EEPROM (non-volatile) |
| Terminal Form | — | PIN/PEG (through-hole PGA) |
| Package Code | — | PGA |
| Temperature Grade | — | Industrial |
| I/O Pin DC Input Range | — | -0.5 V to VCC + 0.5 V |
| Dedicated-Input Pin DC Input Range | — | -0.3 V to VCC + 0.3 V |
| I/O Transient Envelope (no-load, <20 ns) | — | -2.0 V undershoot to 7.0 V overshoot |
| VCC Ramp Requirement | — | Monotonic rise |
| Development Tool | — | Altera MAX+PLUS II |
| Supported HDLs | — | VHDL, Verilog HDL, AHDL |