EPM9560R1208-20 vs EPM9560RI208-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560R1208-20 sa pamamagitan ng Altera at EPM9560RI208-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560R1208-20 EPM9560RI208-20
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 6,000 12,000
Macrocells 560 —
Logic Array Blocks 52 (typical for 560 macrocells) —
Maximum User I/O 212 —
Propagation Delay (tPD) 20 ns —
Maximum Frequency (fMAX) 125 MHz —
Supply Voltage (VCCINT/VCCIO) 5.0 V —
Technology CMOS EEPROM —
In-System Programmability Yes (IEEE 1149.1 JTAG) Yes (IEEE Std. 1149.1 JTAG)
Temperature na Operasyon 0C to +70C (commercial) [DATA_NEEDED: operating temperature range grade]
Packhaging R-1208 (BGA-style fine-pitch) 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm
Uri ng Pagpapasok Surface Mount Surface Mount
Process Technology CMOS EEPROM, third-generation MAX architecture CMOS EEPROM
Architecture Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) Multiple Array MatriX (MAX) - third generation
Boundary-Scan Test JTAG IEEE Std. 1149.1 —
Configuration Memory On-chip EEPROM (non-volatile) —
Tindminan RoHS [DATA_NEEDED: confirm via current distributor data] [DATA_NEEDED: RoHS compliance status]
Macro Cells — 560
Logic Array Blocks (LABs) — 16
Maximum User I/O Pins — 212
Pin-to-Pin Propagation Delay (tPD) — 20 ns
Counter Frequency (fCNT) — 100 MHz
Supply Voltage (VCC) — 5.0 V

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