EPM9560RC208-16 vs EPM9560RC208-18 Comparison

Detailed side-by-side comparison of EPM9560RC208-16 by Intel and EPM9560RC208-18 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9560RC208-18 EPM9560RC208-18 - MAX 9000 CPLD 560 Macro Cells 5V | Altera

EPM9560RC208-18 - MAX 9000 CPLD 560 Macro Cells 5V | Altera

EPM9560RC208-18 ✗ End of Life

Specification Comparison

Parameter EPM9560RC208-16 EPM9560RC208-18
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND End of Life
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Logic Elements / Macrocells 560 macrocells —
Typical Gates 12,000 gates —
Usable Gates 12,000 (typical) 12,000 gates
Pin-to-Pin Delay (tPD) 16 ns —
Maximum Internal Frequency (fMAX) 117.6 MHz —
Supply Voltage (VCCINT / VCCIO) 5 V —
User I/O Pins 416 —
Package 208-pin Power Quad Flat Pack (RQFP) 208-pin RQFP (Power Quad Flat Pack)
Mounting Type Surface Mount Surface Mount
Process Technology 0.35 µm CMOS EEPROM —
Programmability In-system via JTAG (IEEE 1149.1) —
Operating Temperature [DATA_NEEDED: industrial/commercial temperature grade] [DATA_NEEDED: operating temperature range]
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Speed Grade -16 —
Device Family — MAX 9000 (EPM9560)
Logic Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Macrocells — 560 macrocells
Propagation Delay (tPD) — 18 ns (speed grade -18)
Maximum Operating Frequency — 117.6 MHz (family -15 grade reference)
Supply Voltage — 5 V
I/O Voltage Compatibility — 3.3 V or 5 V
User I/O Lines — 149 I/O lines
Flip-Flops — 772 flip-flops
Package JESD-30 Code — S-PQFP-G208
Configuration Memory — EEPROM (non-volatile, no external config PROM)
Technology — CMOS
Lifecycle Status — EOL / mature (per Altera product discontinuance notice)

Datasheets & Resources

Browse All Products Create BOM Request Quote