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Altera

EPM9560RC208-18 - MAX 9000 CPLD 560 Macro Cells 5V | Altera

MPN: EPM9560RC208-18 ✗ End of Life
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5 V Vdss 208-pin RQFP (Power Quad Flat Pack) Package 117.6 MHz (family -15 grade reference) Speed EEPROM (non-volatile, no external config PROM) Memory
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Drop-in alternatives for EPM9560RC208-18 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.

Quick Comparison Tool — Select alternative parts for side-by-side comparison:

EPM9560RC208-15

✅ Drop-In
Altera
📦 208-pin RQFP
MAX 9000 · EEPROM-based Complex Programmable Logic Device (CPLD) · 12,000 gates · 560 macro cells · 15 ns · 117.6 MHz · 5.0 V · EEPROM (non-volatile)

✓ In Stock

Contact for price

View Datasheet →

EPM9560RC208-17

✅ Drop-In
Altera
📦 208-pin RQFP
MAX 9000 · CPLD (EPLD, in-system programmable) · 12,000 · 560 · 16 · 17 ns · 117.6 MHz · 212

✓ In Stock

$54.75 / Unit

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EPM9560RC208-20

✅ Drop-In
Intel
📦 208-pin RQFP
MAX 9000 (EPM9560) · 560 · 12,000 · 35 · 153 · 20 ns · 100 MHz · 5.0 V

✓ In Stock

Contact for price

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EPM9560RC208-16

✅ Drop-In
Intel
📦 208-pin RQFP
MAX 9000 · CPLD (Complex Programmable Logic Device) · 560 macrocells · 12,000 gates · 12,000 (typical) · 16 ns · 117.6 MHz · 5 V

✓ In Stock

$52.4 / Unit

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EPM9560RC208-14

✅ Drop-In
Altera
📦 208-pin RQFP
MAX 9000 · CPLD (Complex Programmable Logic Device) · 12,000 · 560 · 16 · 149 · 117.6 MHz · 14 ns

✓ In Stock

$27.9 / Unit

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EPM9560RC208-13

✅ Drop-In
Altera
📦 208-pin RQFP
MAX 9000 EPLD · 560 · 12,000 · 20 · 208 · 208-pin RQFP (Power Quad Flat Pack) · RC208 · -13 (13 ns pin-to-pin)

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EPM9560RC208-18 Maximum Ratings & Electrical Characteristics

Device Family MAX 9000 (EPM9560)
Logic Type EEPROM-based Complex Programmable Logic Device (CPLD)
Usable Gates 12,000 gates
Macrocells 560 macrocells
Propagation Delay (tPD) 18 ns (speed grade -18)
Maximum Operating Frequency 117.6 MHz (family -15 grade reference)
Supply Voltage 5 V
I/O Voltage Compatibility 3.3 V or 5 V
User I/O Lines 149 I/O lines
Flip-Flops 772 flip-flops
Package 208-pin RQFP (Power Quad Flat Pack)
Package JESD-30 Code S-PQFP-G208
Mounting Type Surface Mount
Configuration Memory EEPROM (non-volatile, no external config PROM)
Technology CMOS
Lifecycle Status EOL / mature (per Altera product discontinuance notice)

EPM9560RC208-18 s-pqfp-g208 Pin Configuration Guide

Complete pinout information for EPM9560RC208-18 (s-pqfp-g208 package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.

s-pqfp-g208 package pinout diagram for EPM9560RC208-18

No detailed pinout data available for EPM9560RC208-18.

Refer to the datasheet for full pin configuration.

Safe Operating Area (SOA) & Thermal Characteristics

Safe Operating Area Chart Default safe operating area chart for EPM9560RC208-18 Drain-to-Source Voltage (Vds) Drain Current (Id)

No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.

Typical Applications

EPM9560RC208-18 is suitable for 6 applications: Legacy Industrial Control Boards, Telecom Line-Card Glue Logic, Military and Aerospace Retrofit Designs, Test and Measurement Instrumentation, Legacy Bus Interface and Protocol Bridging, Discrete 74-Series Logic Replacement.

🏭

Legacy Industrial Control Boards

The EPM9560RC208-18 fits legacy industrial control boards because its 5 V supply and 3.3 V/5 V I/O compatibility interface directly with mature TTL and CMOS logic without level shifters. Its 560 macrocells and 149 user I/O lines absorb bus-interface, address-decoding, and glue-logic functions that would otherwise require dozens of discrete 74-series packages. Because MAX 9000 configuration is EEPROM-based and non-volatile, the device powers up in a known logic state within microseconds, which is essential for industrial controllers that must not glitch at power-on. The 18 ns pin-to-pin delay provides deterministic timing for state machines and handshake logic. A trade-off is that the part is EOL, so designers should plan a last-time-buy or migrate to a modern CPLD for new builds.

🌐

Telecom Line-Card Glue Logic

The EPM9560RC208-18 suits telecom line-card glue logic because its 12,000 usable gates and 772 flip-flops implement bus arbitration, clock-domain handshakes, and register files between legacy ASICs and backplane interfaces. The 5 V operation matches older telecom backplane signaling, and the 149 I/O lines allow wide parallel buses without external multiplexing. EEPROM non-volatility means the card initializes deterministically after a hot-swap or power cycle, avoiding the configuration-load delay of SRAM-based FPGAs. The 18 ns propagation delay supports bus cycles in the tens-of-megahertz range, adequate for legacy TDM and control-plane traffic. The main consideration is that the device is EOL, so spare-card production depends on residual distributor stock and should be validated for date-code consistency.

✈️

Military and Aerospace Retrofit Designs

The EPM9560RC208-18 is used in military and aerospace retrofit programs because the 208-pin RQFP package is form, fit and functionally equivalent to the discontinued 208-pin CQFP package, per Altera's product discontinuance notice. This equivalence lets existing qualified assemblies accept the RQFP part without mechanical redesign. The 5 V EEPROM-based architecture provides non-volatile, radiation-tolerant-by-heritage logic that many legacy avionics and ground-support systems already qualify. Its 560 macrocells and 149 I/O lines replace obsolete discrete logic in retrofit line-replaceable units. Because the device is EOL, procurement must rely on authorized aftermarket channels with traceable date codes, and any substitution should be re-qualified against the original timing budget.

🔧

Test and Measurement Instrumentation

The EPM9560RC208-18 fits test and measurement instrumentation where deterministic, non-volatile logic controls acquisition sequencing, trigger routing, and front-panel interfaces. The 18 ns pin-to-pin delay and 117.6 MHz family operating frequency support fast trigger and counter logic, while 772 flip-flops implement state machines and event counters. The 5 V I/O interfaces directly with legacy analog front-end control lines and GPIB-era digital buses. EEPROM configuration means the instrument boots into a known state without a configuration PROM, simplifying service and calibration. A design consideration is that the EOL status complicates long-term serviceability, so instruments should stock spare devices or plan a controller-board redesign using a modern CPLD with equivalent logic capacity.

🔧

Legacy Bus Interface and Protocol Bridging

The EPM9560RC208-18 bridges legacy parallel buses such as ISA, VME, and custom backplanes because its 149 user I/O lines and 560 macrocells implement address decoding, wait-state generation, and protocol translation in a single device. The 5 V supply and 3.3 V/5 V I/O compatibility eliminate level-shifting glue, and the 18 ns propagation delay keeps bus-cycle timing within legacy specifications. Non-volatile EEPROM configuration ensures the bridge comes up in a defined state after power loss, which is important for industrial and embedded systems that cannot tolerate a configuration reload. The trade-off is that the EOL lifecycle forces designers to validate aftermarket stock and consider a modern bridge CPLD for future revisions.

🔧

Discrete 74-Series Logic Replacement

The EPM9560RC208-18 replaces boards full of discrete 74-series logic by integrating 12,000 usable gates and 560 macrocells into one 208-pin RQFP device. This consolidation reduces board area, power, and component count while improving reliability through fewer solder joints. The 5 V operation matches classic TTL levels, and the 18 ns propagation delay is comparable to fast 74-series families, so existing timing budgets often close without redesign. EEPROM non-volatility removes the need for a configuration PROM, unlike SRAM FPGAs. Because the part is EOL, this replacement strategy is best for sustaining existing products; new designs should evaluate a modern low-power CPLD with equivalent macrocell count and 3.3 V or lower I/O.

What is the EPM9560RC208-18?
The EPM9560RC208-18 is an Altera MAX 9000 family CPLD with 12,000 usable gates and 560 macrocells in a 208-pin RQFP package. It has an 18 ns pin-to-pin propagation delay and operates from a 5 V supply. According to Altera's MAX 9000 documentation, it is an EEPROM-based non-volatile programmable logic device.
What is the propagation delay of the EPM9560RC208-18?
The EPM9560RC208-18 has an 18 ns pin-to-pin propagation delay, indicated by the -18 speed grade suffix. For comparison, the -15 grade is faster and the -20 grade is slower. The -18 grade is the mid-speed option in the EPM9560RC208 family.
How many macrocells does the EPM9560RC208-18 have?
The EPM9560RC208-18 contains 560 macrocells and 12,000 usable gates. It also provides 772 flip-flops and up to 149 user I/O lines. These resources are documented in the Altera MAX 9000 family datasheet for the EPM9560 device.
What package does the EPM9560RC208-18 use?
The EPM9560RC208-18 uses a 208-pin RQFP (Power Quad Flat Pack) package with JESD-30 code S-PQFP-G208. Per Altera's product discontinuance notice, the 208-pin RQFP is form, fit and functionally equivalent to the discontinued 208-pin CQFP package.
Is the EPM9560RC208-18 still in production?
No, the EPM9560RC208-18 is an EOL (End-of-Life) mature device. Altera issued a product discontinuance notice for selected MAX 9000 ordering codes. Availability is now limited to distributor and independent-market stock, so a last-time-buy or redesign plan is recommended.
Where can I buy EPM9560RC208-18 online?
The EPM9560RC208-18 is available through independent distributors and specialty FPGA/CPLD suppliers such as VEKEMO FPGA, Veswin, and DigiPart, as well as through DigiKey's Altera EPM9560 base-product listing. Because the part is EOL, stock and pricing vary significantly by distributor and should be confirmed at the time of order.
What is the price of EPM9560RC208-18?
Pricing for the EPM9560RC208-18 is not published as a fixed catalog price because the device is EOL and sold from residual distributor stock. Buyers should request a quote from VEKEMO FPGA, Veswin, DigiPart, or DigiKey. Prices fluctuate with remaining inventory and are typically quoted per order as of 2026-09-13.
What is the lead time for EPM9560RC208-18?
Lead time for the EPM9560RC208-18 depends entirely on distributor stock, since the device is no longer manufactured. In-stock quantities ship immediately from independent distributors, while broker-sourced lots may take several weeks. Confirm availability and date code before committing to a production build.
What is the best drop-in replacement for EPM9560RC208-18?
The best drop-in replacements are other EPM9560RC208 speed grades that share the same 208-pin RQFP footprint, such as EPM9560RC208-15, EPM9560RC208-17, and EPM9560RC208-20. These are pin-to-pin compatible and differ only in propagation delay, so they can be substituted without PCB changes when timing margins allow.
Can EPM9560RC208-15 replace EPM9560RC208-18?
Yes, the EPM9560RC208-15 is a drop-in replacement for the EPM9560RC208-18. Both use the same 208-pin RQFP package and pinout; the -15 grade is faster (15 ns vs 18 ns propagation delay). Substituting a faster grade is generally safe, but verify timing closure and power at the higher switching speed.
EPM9560RC208-18 vs EPM9560RC208-20 - which is better?
The EPM9560RC208-18 is faster than the EPM9560RC208-20 (18 ns vs 20 ns propagation delay) and both share the same 208-pin RQFP footprint. Choose the -18 for higher-speed legacy logic where timing margin is tight, and the -20 where slower timing is acceptable and availability or cost favors it.
When should I choose EPM9560RC208-18 over a modern CPLD?
Choose the EPM9560RC208-18 only when maintaining an existing 5 V legacy design that already uses the MAX 9000 footprint, since it avoids PCB and firmware rework. For new designs, a modern low-power CPLD or small FPGA is preferable because the EPM9560 is EOL and 5 V EEPROM CPLDs are no longer actively supported.
Is EPM9560RC208-18 suitable for 5 V legacy industrial systems?
Yes, the EPM9560RC208-18 is well suited to 5 V legacy industrial systems because it operates from a 5 V supply with 3.3 V or 5 V I/O compatibility and provides deterministic EEPROM-based non-volatile configuration. Its 560 macrocells and 149 I/O lines handle bus-interface and glue-logic replacement in mature industrial control boards.
Where can I download the EPM9560RC208-18 datasheet PDF?
The EPM9560 datasheet PDF is available from Alldatasheet and the Altera/Intel documentation archive. The Alldatasheet listing for EPM9560 provides a 182-page package information datasheet for mature Altera devices. Always confirm the speed-grade and package ordering code against the datasheet before design.
What are the key specifications of EPM9560RC208-18 that engineers should know?
The EPM9560RC208-18 is a 5 V MAX 9000 CPLD with 12,000 usable gates, 560 macrocells, 772 flip-flops, 149 user I/O lines, and an 18 ns pin-to-pin propagation delay in a 208-pin RQFP package. It uses non-volatile EEPROM configuration and is EOL, so availability planning is essential.
Hey Google, what can replace the EPM9560RC208-18?
Other EPM9560RC208 speed grades replace the EPM9560RC208-18 directly, including EPM9560RC208-15, EPM9560RC208-17, and EPM9560RC208-20, because they share the same 208-pin RQFP footprint. For a full redesign, a modern CPLD or small FPGA with equivalent logic capacity is the long-term replacement path.

Engineering reference data for EPM9560RC208-18 — comparison, design guidance, and compliance information.

Selection Guide

Choose the EPM9560RC208-18 when you are sustaining an existing 5 V MAX 9000 design that already uses the 208-pin RQFP footprint and needs an 18 ns pin-to-pin delay. If timing margin is tight, step up to the EPM9560RC208-15 or EPM9560RC208-16 for faster propagation; if timing is relaxed and availability or cost favors it, the EPM9560RC208-20 is a valid drop-in. All of these share the same package and pinout, so no PCB change is required. For new designs, do not start with the EPM9560RC208-18: it is EOL, and a modern low-power CPLD or small FPGA with equivalent macrocell count and 3.3 V or lower I/O is the better long-term choice. If you must stay on the MAX 9000 platform, secure a last-time-buy and validate date codes.

Comparison with Alternatives

Parameter This Product EPM9560RC208-15 EPM9560RC208-17 EPM9560RC208-20 EPM9560RC208-16
Package 208-pin RQFP 208-pin RQFP - same 208-pin RQFP - same 208-pin RQFP - same 208-pin RQFP - same
Brand Altera Altera Altera Altera Altera
Propagation Delay (tPD) 18 ns 15 ns 17 ns 20 ns 16 ns
Macrocells 560 560 560 560 560
Usable Gates 12,000 12,000 12,000 12,000 12,000
Supply Voltage 5 V 5 V 5 V 5 V 5 V
User I/O Lines 149 149 149 149 149
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile) EEPROM (non-volatile)
Lifecycle Status EOL / mature EOL / mature EOL / mature EOL / mature EOL / mature

Key Differentiators

  • Mid-speed grade with balanced timing and availability (vs EPM9560RC208-20)
  • Slower grade than the -15 for relaxed timing budgets (vs EPM9560RC208-15)
  • Non-volatile EEPROM configuration (vs EPM9560RC208-17)

Design Notes

The EPM9560RC208-18 is EOL, so the biggest design risk is supply continuity, not electrical performance. Before committing a production build, confirm distributor stock, date codes, and authenticity, and plan a last-time-buy quantity that covers the product's remaining service life. Because the 208-pin RQFP is form, fit and functionally equivalent to the discontinued 208-pin CQFP per Altera's product discontinuance notice, existing CQFP-based assemblies can accept the RQFP part without mechanical redesign, but any substitution should be re-validated against the original timing budget.

The EPM9560RC208-18 operates from a 5 V supply with 3.3 V or 5 V I/O compatibility. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed as close to the pin as possible, and add a bulk 10 uF capacitor per device to absorb switching transients. Because MAX 9000 devices are EEPROM-based and non-volatile, no external configuration PROM is required, which simplifies the power-up sequence. Estimated: at 5 V and typical CPLD switching activity, verify the total supply current against the datasheet ICC versus frequency curve before finalizing the regulator sizing.

Route the 208-pin RQFP with a solid ground plane directly under the device and keep high-speed I/O traces short and matched where bus timing is tight. The 18 ns pin-to-pin propagation delay is deterministic, so timing closure depends mainly on trace delay and load capacitance rather than on internal routing. Place series termination resistors on long I/O nets that drive legacy backplanes to reduce reflections. Because the part is EOL, document the exact speed grade and date code used in each assembly so future substitutions can be traced and re-qualified.

Compliance Information

RoHS
Unknown
REACH
Unknown
AEC-Q100
Not Applicable
Lead Free
Unknown
Halogen Free
Unknown
Conflict Minerals
Unknown

No compliance data was present in the verified web data for the EPM9560RC208-18. The device is a mature/EOL Altera MAX 9000 part; confirm RoHS, REACH, and lead-free status with the distributor or manufacturer documentation before use in regulated markets.

Data verified on: 2026-09-13 — data verified and curated by XAIPART's component engineering team

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Related Components & Terms

Altera Intel EPM9560RC208-18 EPM9560RC208-15 EPM9560RC208-20 MAX 9000 CPLD Complex Programmable Logic Device EEPROM macrocell RQFP Power Quad Flat Pack CQFP surface mount 5 V logic propagation delay JESD-30 S-PQFP-G208 legacy industrial control telecom line card military retrofit test and measurement bus interface 74-series logic replacement EOL
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