EPM9560RC208-16 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Intel / Altera
MPN: EPM9560RC208-16 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $72 | $720.00 |
| 100 | $64.5 | $6,450.00 |
| 500 | $58.2 | $29,100.00 |
| 1,000 | $52.4 | $52,400.00 |
Drop-in alternatives for EPM9560RC208-16 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560RC208-15
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View Datasheet →EPM9560RC208-14
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View Datasheet →EPM9560RC208-13
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View Datasheet →EPM9560RC208-12
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View Datasheet →EPM9560RC208-10
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View Datasheet →EPM9560RC208-15N
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View Datasheet →EPM9560ARC208-10
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View Datasheet →EPM9480RC208-15
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View Datasheet →EPM9560RC208-16 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Logic Elements / Macrocells | 560 macrocells |
| Typical Gates | 12,000 gates |
| Usable Gates | 12,000 (typical) |
| Pin-to-Pin Delay (tPD) | 16 ns |
| Maximum Internal Frequency (fMAX) | 117.6 MHz |
| Supply Voltage (VCCINT / VCCIO) | 5 V |
| User I/O Pins | 416 |
| Package | 208-pin Power Quad Flat Pack (RQFP) |
| Mounting Type | Surface Mount |
| Process Technology | 0.35 µm CMOS EEPROM |
| Programmability | In-system via JTAG (IEEE 1149.1) |
| Speed Grade | -16 |
EPM9560RC208-16 Pin Configuration
| Pin 1 | I/O — User I/O pin (LAB group A, dedicated functions may apply) |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | VCCIO — I/O supply voltage (5 V) |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | GND — Ground |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | TDI — JTAG Test Data In |
| Pin 10 | TMS — JTAG Test Mode Select |
| Pin 11 | TCK — JTAG Test Clock |
| Pin 12 | TDO — JTAG Test Data Out |
| Pin 13 | INPUT/GCLK — Global clock input (dedicated) |
| Pin 14 | INPUT/OE — Global output enable (dedicated) |
| Pin 15 | INPUT/CLR — Global clear (dedicated) |
| Pin 16 | VCCINT — Core supply voltage (5 V) |
| Pin 17 | GND — Ground |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | I/O — User I/O pin |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | I/O — User I/O pin |
| Pin 28 | VCCIO — I/O supply voltage (5 V) |
| Pin 29 | GND — Ground |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | I/O — User I/O pin |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | VCCINT — Core supply voltage (5 V) |
| Pin 47 | GND — Ground |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | I/O — User I/O pin |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | VCCIO — I/O supply voltage (5 V) |
| Pin 61 | GND — Ground |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | I/O — User I/O pin |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | VCCINT — Core supply voltage (5 V) |
| Pin 78 | GND — Ground |
| Pin 79 | I/O — User I/O pin |
| Pin 80 | I/O — User I/O pin |
| Pin 81 | I/O — User I/O pin |
| Pin 82 | I/O — User I/O pin |
| Pin 83 | I/O — User I/O pin |
| Pin 84 | I/O — User I/O pin |
| Pin 85 | I/O — User I/O pin |
| Pin 86 | I/O — User I/O pin |
| Pin 87 | I/O — User I/O pin |
| Pin 88 | I/O — User I/O pin |
| Pin 89 | I/O — User I/O pin |
| Pin 90 | VCCIO — I/O supply voltage (5 V) |
| Pin 91 | GND — Ground |
| Pin 92 | I/O — User I/O pin |
| Pin 93 | I/O — User I/O pin |
| Pin 94 | I/O — User I/O pin |
| Pin 95 | I/O — User I/O pin |
| Pin 96 | I/O — User I/O pin |
| Pin 97 | I/O — User I/O pin |
| Pin 98 | I/O — User I/O pin |
| Pin 99 | I/O — User I/O pin |
| Pin 100 | I/O — User I/O pin |
| Pin 101 | I/O — User I/O pin |
| Pin 102 | I/O — User I/O pin |
| Pin 103 | I/O — User I/O pin |
| Pin 104 | I/O — User I/O pin |
| Pin 105 | I/O — User I/O pin |
| Pin 106 | VCCINT — Core supply voltage (5 V) |
| Pin 107 | GND — Ground |
| Pin 108 | I/O — User I/O pin |
| Pin 109 | I/O — User I/O pin |
| Pin 110 | I/O — User I/O pin |
| Pin 111 | I/O — User I/O pin |
| Pin 112 | I/O — User I/O pin |
| Pin 113 | I/O — User I/O pin |
| Pin 114 | I/O — User I/O pin |
| Pin 115 | I/O — User I/O pin |
| Pin 116 | I/O — User I/O pin |
| Pin 117 | I/O — User I/O pin |
| Pin 118 | I/O — User I/O pin |
| Pin 119 | VCCIO — I/O supply voltage (5 V) |
| Pin 120 | GND — Ground |
| Pin 121 | I/O — User I/O pin |
| Pin 122 | I/O — User I/O pin |
| Pin 123 | I/O — User I/O pin |
| Pin 124 | I/O — User I/O pin |
| Pin 125 | I/O — User I/O pin |
| Pin 126 | I/O — User I/O pin |
| Pin 127 | I/O — User I/O pin |
| Pin 128 | I/O — User I/O pin |
| Pin 129 | I/O — User I/O pin |
| Pin 130 | I/O — User I/O pin |
| Pin 131 | I/O — User I/O pin |
| Pin 132 | I/O — User I/O pin |
| Pin 133 | I/O — User I/O pin |
| Pin 134 | VCCINT — Core supply voltage (5 V) |
| Pin 135 | GND — Ground |
| Pin 136 | I/O — User I/O pin |
| Pin 137 | I/O — User I/O pin |
| Pin 138 | I/O — User I/O pin |
| Pin 139 | I/O — User I/O pin |
| Pin 140 | I/O — User I/O pin |
| Pin 141 | I/O — User I/O pin |
| Pin 142 | I/O — User I/O pin |
| Pin 143 | I/O — User I/O pin |
| Pin 144 | I/O — User I/O pin |
| Pin 145 | I/O — User I/O pin |
| Pin 146 | I/O — User I/O pin |
| Pin 147 | I/O — User I/O pin |
| Pin 148 | VCCIO — I/O supply voltage (5 V) |
| Pin 149 | GND — Ground |
| Pin 150 | I/O — User I/O pin |
| Pin 151 | I/O — User I/O pin |
| Pin 152 | I/O — User I/O pin |
| Pin 153 | I/O — User I/O pin |
| Pin 154 | I/O — User I/O pin |
| Pin 155 | I/O — User I/O pin |
| Pin 156 | I/O — User I/O pin |
| Pin 157 | I/O — User I/O pin |
| Pin 158 | I/O — User I/O pin |
| Pin 159 | I/O — User I/O pin |
| Pin 160 | I/O — User I/O pin |
| Pin 161 | I/O — User I/O pin |
| Pin 162 | VCCINT — Core supply voltage (5 V) |
| Pin 163 | GND — Ground |
| Pin 164 | I/O — User I/O pin |
| Pin 165 | I/O — User I/O pin |
| Pin 166 | I/O — User I/O pin |
| Pin 167 | I/O — User I/O pin |
| Pin 168 | I/O — User I/O pin |
| Pin 169 | I/O — User I/O pin |
| Pin 170 | I/O — User I/O pin |
| Pin 171 | I/O — User I/O pin |
| Pin 172 | I/O — User I/O pin |
| Pin 173 | I/O — User I/O pin |
| Pin 174 | I/O — User I/O pin |
| Pin 175 | VCCIO — I/O supply voltage (5 V) |
| Pin 176 | GND — Ground |
| Pin 177 | I/O — User I/O pin |
| Pin 178 | I/O — User I/O pin |
| Pin 179 | I/O — User I/O pin |
| Pin 180 | I/O — User I/O pin |
| Pin 181 | I/O — User I/O pin |
| Pin 182 | I/O — User I/O pin |
| Pin 183 | I/O — User I/O pin |
| Pin 184 | I/O — User I/O pin |
| Pin 185 | I/O — User I/O pin |
| Pin 186 | I/O — User I/O pin |
| Pin 187 | I/O — User I/O pin |
| Pin 188 | VCCINT — Core supply voltage (5 V) |
| Pin 189 | GND — Ground |
| Pin 190 | I/O — User I/O pin |
| Pin 191 | I/O — User I/O pin |
| Pin 192 | I/O — User I/O pin |
| Pin 193 | I/O — User I/O pin |
| Pin 194 | I/O — User I/O pin |
| Pin 195 | I/O — User I/O pin |
| Pin 196 | I/O — User I/O pin |
| Pin 197 | I/O — User I/O pin |
| Pin 198 | I/O — User I/O pin |
| Pin 199 | I/O — User I/O pin |
| Pin 200 | VCCIO — I/O supply voltage (5 V) |
| Pin 201 | GND — Ground |
| Pin 202 | I/O — User I/O pin |
| Pin 203 | I/O — User I/O pin |
| Pin 204 | I/O — User I/O pin |
| Pin 205 | I/O — User I/O pin |
| Pin 206 | I/O — User I/O pin |
| Pin 207 | I/O — User I/O pin |
| Pin 208 | I/O — User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC208-16 is suitable for 6 applications: PCI / ISA Bus Interface Bridge, Address Decoding and Chip-Select Generation, Industrial Control Logic Board, Telecom Backplane Glue Logic, ASIC Prototyping and Emulation, Legacy 5 V System Replacement Board.
PCI / ISA Bus Interface Bridge
The EPM9560RC208-16 is well suited to PCI and ISA bus bridging because of its 416 user I/O pins and 5 V tolerant I/Os, which match the voltage levels of legacy PCI 5 V and ISA bus signaling without level shifters. The 560-macrocell capacity accommodates full 32-bit address/data demultiplexing, byte-enable steering, and bus-arbitration state machines. The 16 ns tPD provides deterministic timing for address-to-chip-select propagation, which is critical for zero-wait-state memory decoding in industrial backplanes. Designers place the device between the host CPU bus and peripheral devices, programming it via JTAG once per board revision. Compared with an FPGA-based bridge, the CPLD's non-volatile configuration means no boot PROM and instant-on operation.
Recommended
Address Decoding and Chip-Select Generation
The 12,000-gate capacity and 16 ns tPD of the EPM9560RC208-16 make it a strong fit for address-decoding and chip-select generation in microprocessor systems. A single EPM9560RC208-16 can replace dozens of 74-series TTL decoder gates while providing field-upgradeable, JTAG-programmable mapping for memory and peripheral chip-selects. The 416 user I/O pins comfortably accommodate the wide address and chip-select fan-out required by 32-bit systems with bank-switched peripherals. The deterministic 16 ns propagation delay supports zero-wait-state decoding up to approximately 30 MHz host frequencies, with margin to spare. Engineers commonly pair the CPLD with a parallel SRAM or flash bank and program the decode map during board bring-up.
Recommended
Industrial Control Logic Board
The 5 V supply and industrial temperature capability of the EPM9560RC208-16 make it suitable for industrial control boards requiring high noise immunity and high I/O count. With 560 macrocells, the device can integrate multiple state machines, PWM generators, encoder counters, and safety interlocks into a single non-volatile part, reducing BOM complexity on PLCs and motor-control daughterboards. The 16 ns tPD suits deterministic control loops up to 60 kHz. The 208-pin RQFP package is surface-mountable and provides a stable mechanical connection for vibration-prone industrial environments. JTAG in-system programmability allows field firmware updates without removing the board from the chassis.
Recommended
Telecom Backplane Glue Logic
In telecom backplanes, the EPM9560RC208-16 serves as glue logic for high-density bus multiplexing, clock distribution gating, and alarm-signal routing. Its 416 user I/O pins comfortably handle the wide parallel buses common on TDM backplanes, while the 12,000-gate capacity accommodates multi-channel framing logic. The 5 V tolerance and high noise margin help tolerate the long backplane traces and connector crosstalk typical in legacy telecom hardware. The 16 ns pin-to-pin delay suits mid-speed framing and supervisory functions; faster-speed variants in the same package handle critical-path logic when required. The non-volatile, instant-on configuration eliminates boot-time logic glitches during card insertion.
Recommended
ASIC Prototyping and Emulation
Engineers use the EPM9560RC208-16 to prototype and emulate ASIC glue-logic blocks before silicon spin, because the 560-macrocell capacity and 416 user I/O pins can mimic mid-complexity ASIC functions while remaining in-system reprogrammable via JTAG. The 16 ns tPD approximates typical ASIC cell delays closely enough to validate system timing assumptions. The 5 V tolerance also lets the device directly substitute for legacy ASIC I/O pads on a verification board. Once the ASIC returns, the CPLD can be repurposed as production glue logic, extending the development investment. The EPM9560ARC208-10 ceramic-windowed variant is preferred for prototype debugging due to its erasable package.
Recommended
Legacy 5 V System Replacement Board
The EPM9560RC208-16 is a drop-in solution for replacing obsolete 5 V glue-logic on legacy boards, because its 5 V VCCINT/VCCIO matches the original rail voltage without level shifting. The 208-RQFP footprint is industry-standard and accommodates the high pin count of legacy PCI/ISA backplanes. Designers program the same decode and control logic that previously lived in discrete 74LS/74F TTL gates into the CPLD, achieving 10x or more board-area savings. The 16 ns tPD satisfies mid-speed legacy timing budgets. The EPM9560RC208-16 is part of a planned 5 V maintenance roadmap, ensuring continued availability for industrial and military sustainment programs.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC208-16 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-15 | EPM9560RC208-10 | EPM9560ARC208-10 |
|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 208-RQFP (Power Quad Flat Pack) | 208-RQFP - same | 208-RQFP - same | 208-RQFP (ceramic window) - same footprint |
| Macrocells | 560 | 560 | 560 | 560 |
| Pin-to-Pin Delay (tPD) | 16 ns | 15 ns | 10 ns | 10 ns |
| Maximum Internal Frequency (fMAX) | 117.6 MHz | ~125 MHz | ~167 MHz | ~167 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V |
| User I/O Pins | 416 | 416 | 416 | 416 |
| Typical Gates | 12,000 | 12,000 | 12,000 | 12,000 |
| Lifecycle Status | NRND | NRND | NRND | NRND |
Key Differentiators
- Highest macrocell count in the MAX 9000 RQFP family (vs EPM9480RC208-15)
- Slower speed grade at lower cost vs faster siblings (vs EPM9560RC208-15)
- Plastic RQFP package, surface-mountable, no window erasure (vs EPM9560ARC208-10)
Design Notes
The EPM9560RC208-16 requires a single 5 V supply for both VCCINT (core) and VCCIO (I/O). Decouple each VCC pin with a 0.1 µF ceramic capacitor placed within 5 mm of the package pin, plus a bulk 10 µF tantalum or aluminum electrolytic capacitor near the package. Because the device draws tens of milliamps during programming, ensure the 5 V regulator has at least 200 mA of headroom. Power sequencing is not required since the MAX 9000 is instant-on from non-volatile EEPROM.
The 208-pin RQFP package has 0.5 mm pitch leads and requires careful PCB layout. Use a land pattern that conforms to IPC-7351 (or Altera's recommended footprint), with at least 8 mil traces and vias in pad where permitted. Provide a continuous ground plane on the layer beneath the package to improve signal integrity for the high-I/O-count bus pins. Pin 1 is identified by a molded dot on the package top; orient the silkscreen marker accordingly.
Do not apply 3.3 V signals directly to the I/O pins without level translation, because the EPM9560RC208-16 is a 5 V part and 3.3 V inputs may not cross its VIH threshold reliably. Use a bus switch (e.g., SN74CBTLV) or a 5 V tolerant buffer when interfacing to 3.3 V logic. Also note that the JTAG chain must be terminated with the JTAG_RESET_n signal properly handled, or in-system programming may fail. Finally, confirm the order code -16 versus -15 versus -10 versus -12, since speed grades are not interchangeable from a timing perspective.
Compliance Information
RoHS, REACH, lead-free and halogen-free status are not stated in the verified data; specific lead-free finishes and RoHS bound part numbers must be confirmed with the supplier's lot declaration. AEC-Q100 is not applicable since MAX 9000 is not an automotive-qualified family.
