EPM9560RC208-18 vs EPM9560RC208-13 Comparison
Detailed side-by-side comparison of EPM9560RC208-18 by Altera and EPM9560RC208-13 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-18 | EPM9560RC208-13 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | End of Life | Obsolete |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 EPLD |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 gates | 12,000 |
| Macrocells | 560 macrocells | 560 |
| Propagation Delay (tPD) | 18 ns (speed grade -18) | 13 ns |
| Maximum Operating Frequency | 117.6 MHz (family -15 grade reference) | — |
| Supply Voltage | 5 V | 5.0 V |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| User I/O Lines | 149 I/O lines | — |
| Flip-Flops | 772 flip-flops | — |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Package JESD-30 Code | S-PQFP-G208 | — |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile, no external config PROM) | — |
| Technology | CMOS | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lifecycle Status | EOL / mature (per Altera product discontinuance notice) | — |
| Logic Array Blocks (LABs) | — | 20 |
| User I/O Pins | — | 208 |
| Package Code | — | RC208 |
| Speed Grade | — | -13 (13 ns pin-to-pin) |
| Maximum Clock Frequency | — | 125 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| Programming Interface | — | IEEE 1149.1 JTAG |
| Operating Temperature Range | — | 0C to +70C (commercial) |
| Lead-Free Status | — | [DATA_NEEDED: lead-free status] |
| MSL Level | — | [DATA_NEEDED: MSL level] |