EPM9560RC208-18 vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560RC208-18 by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-18 | EPM9560RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Eol | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $0.00 |
| Device Family | MAX 9000 (EPM9560) | β |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | β |
| Usable Gates | 12,000 gates | 12,000 gates |
| Macrocells | 560 macrocells | β |
| Propagation Delay (tPD) | 18 ns (speed grade -18) | β |
| Maximum Operating Frequency | 117.6 MHz (family -15 grade reference) | β |
| Supply Voltage | 5 V | 5.0 V |
| I/O Voltage Compatibility | 3.3 V or 5 V | β |
| User I/O Lines | 149 I/O lines | β |
| Flip-Flops | 772 flip-flops | β |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Package JESD-30 Code | S-PQFP-G208 | β |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile, no external config PROM) | β |
| Technology | CMOS | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lifecycle Status | EOL / mature (per Altera product discontinuance notice) | β |
| Family | β | MAX 9000 |
| Device Type | β | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | β | 560 macro cells |
| Pin-to-Pin Delay | β | 15 ns |
| Counter Speed | β | 117.6 MHz |
| Configuration Technology | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | β | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | β | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | β | -15 (15 ns pin-to-pin) |
| Architecture | β | Third-generation Multiple Array MatriX (MAX) |