EPM9560RC208-18 vs EPM9560RC208-15 Сравнение
Подробное сравнение бок о бок EPM9560RC208-18 от Altera и EPM9560RC208-15 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Altera
EPM9560RC208-18 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
EPM9560RC208-18 ✗ Снят с производстваСравнение характеристик
| Параметр | EPM9560RC208-18 | EPM9560RC208-15 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Снято с производства | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $0,00 | $0,00 |
| Device Family | MAX 9000 (EPM9560) | — |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 gates | 12,000 gates |
| Macrocells | 560 macrocells | — |
| Propagation Delay (tPD) | 18 ns (speed grade -18) | — |
| Maximum Operating Frequency | 117.6 MHz (family -15 grade reference) | — |
| Напряжение питания | 5 V | 5.0 V |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| User I/O Lines | 149 I/O lines | — |
| Flip-Flops | 772 flip-flops | — |
| Корпус | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Package JESD-30 Code | S-PQFP-G208 | — |
| Тип монтажа | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile, no external config PROM) | — |
| Technology | CMOS | — |
| Рабочая температура | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Статус RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Статус жизненного цикла | EOL / mature (per Altera product discontinuance notice) | — |
| Family | — | MAX 9000 |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |