EPM9560RC208-18 vs EPM9560RC208-16 Comparison
Detailed side-by-side comparison of EPM9560RC208-18 by Altera and EPM9560RC208-16 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC208-18
EPM9560RC208-18 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
EPM9560RC208-18 β End of LifeIntel
EPM9560RC208-16
EPM9560RC208-16 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Intel / Altera
EPM9560RC208-16 NrndSpecification Comparison
| Parameter | EPM9560RC208-18 | EPM9560RC208-16 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Eol | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $52.40 |
| Device Family | MAX 9000 (EPM9560) | β |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | β |
| Usable Gates | 12,000 gates | 12,000 (typical) |
| Macrocells | 560 macrocells | β |
| Propagation Delay (tPD) | 18 ns (speed grade -18) | β |
| Maximum Operating Frequency | 117.6 MHz (family -15 grade reference) | β |
| Supply Voltage | 5 V | β |
| I/O Voltage Compatibility | 3.3 V or 5 V | β |
| User I/O Lines | 149 I/O lines | β |
| Flip-Flops | 772 flip-flops | β |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin Power Quad Flat Pack (RQFP) |
| Package JESD-30 Code | S-PQFP-G208 | β |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile, no external config PROM) | β |
| Technology | CMOS | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temperature grade] |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lifecycle Status | EOL / mature (per Altera product discontinuance notice) | β |
| Family | β | MAX 9000 |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Elements / Macrocells | β | 560 macrocells |
| Typical Gates | β | 12,000 gates |
| Pin-to-Pin Delay (tPD) | β | 16 ns |
| Maximum Internal Frequency (fMAX) | β | 117.6 MHz |
| Supply Voltage (VCCINT / VCCIO) | β | 5 V |
| User I/O Pins | β | 416 |
| Process Technology | β | 0.35 Β΅m CMOS EEPROM |
| Programmability | β | In-system via JTAG (IEEE 1149.1) |
| Speed Grade | β | -16 |