EPM9560RC208-18 vs EPM9560RC208-16 Comparison
Detailed side-by-side comparison of EPM9560RC208-18 by Altera and EPM9560RC208-16 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RC208-16 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Intel / Altera
EPM9560RC208-16 NrndSpecification Comparison
| Parameter | EPM9560RC208-18 | EPM9560RC208-16 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | End of Life | NRND |
| Device Family | MAX 9000 (EPM9560) | — |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 gates | 12,000 (typical) |
| Macrocells | 560 macrocells | — |
| Propagation Delay (tPD) | 18 ns (speed grade -18) | — |
| Maximum Operating Frequency | 117.6 MHz (family -15 grade reference) | — |
| Supply Voltage | 5 V | — |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| User I/O Lines | 149 I/O lines | — |
| Flip-Flops | 772 flip-flops | — |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin Power Quad Flat Pack (RQFP) |
| Package JESD-30 Code | S-PQFP-G208 | — |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile, no external config PROM) | — |
| Technology | CMOS | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: industrial/commercial temperature grade] |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lifecycle Status | EOL / mature (per Altera product discontinuance notice) | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements / Macrocells | — | 560 macrocells |
| Typical Gates | — | 12,000 gates |
| Pin-to-Pin Delay (tPD) | — | 16 ns |
| Maximum Internal Frequency (fMAX) | — | 117.6 MHz |
| Supply Voltage (VCCINT / VCCIO) | — | 5 V |
| User I/O Pins | — | 416 |
| Process Technology | — | 0.35 µm CMOS EEPROM |
| Programmability | — | In-system via JTAG (IEEE 1149.1) |
| Speed Grade | — | -16 |