EPM9560RC208-3 vs EPM9560RC208-17 Comparison
Detailed side-by-side comparison of EPM9560RC208-3 by Altera and EPM9560RC208-17 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-3 | EPM9560RC208-17 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates | 12,000 | 12,000 |
| Maximum Operating Frequency | [DATA_NEEDED: f_MAX] | — |
| Pin-to-Pin Delay (speed grade -3) | approximately 3 ns (slowest grade) | — |
| Speed Grade | -3 | — |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (RC208) |
| I/O Voltage Tolerance | 5V | — |
| Process Technology | 0.5 µm CMOS EPROM | — |
| Programming Interface | ByteBlaster / BitBlaster (JTAG-compatible) | — |
| Operating Temperature | [DATA_NEEDED: industrial / commercial range] | — |
| RoHS Status | [DATA_NEEDED] | — |
| Lifecycle | Mature / Last-time-buy (per Altera PDN for selected MAX 9000 ordering codes) | — |
| Product Type | — | CPLD (EPLD, in-system programmable) |
| Macro Cells | — | 560 |
| Pin-to-Pin Delay (tPD) | — | 17 ns |
| Maximum Counter Frequency | — | 117.6 MHz |
| User I/O Pins | — | 212 |
| Supply Voltage (VCC) | — | 5 V |
| Programming Technology | — | EEPROM (in-system programmable) |
| Program/Erase Cycles | — | 100 minimum |
| JTAG (IEEE 1149.1) Support | — | Yes |
| Architecture | — | Third-generation MAX (AND-OR PLA) |
| Mounting Type | — | Surface Mount |