EPM9560RC208-17 - MAX 9000 CPLD 12K Gates 560 Macro Cells | Altera
MPN: EPM9560RC208-17 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $82.5 | $825.00 |
| 100 | $70 | $7,000.00 |
| 500 | $61.2 | $30,600.00 |
| 1,000 | $54.75 | $54,750.00 |
Drop-in alternatives for EPM9560RC208-17 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RC208-15
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View Datasheet βEPM9560RC208-20
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View Datasheet βEPM9560RC208-12
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View Datasheet βEPM9560RC208-15N
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$19.85 / Unit
View Datasheet βEPM9560RC208-16
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$52.4 / Unit
View Datasheet βEPM9560RC208-17 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Product Type | CPLD (EPLD, in-system programmable) |
| Usable Gates | 12,000 |
| Macro Cells | 560 |
| Logic Array Blocks (LABs) | 16 |
| Pin-to-Pin Delay (tPD) | 17 ns |
| Maximum Counter Frequency | 117.6 MHz |
| User I/O Pins | 212 |
| Supply Voltage (VCC) | 5 V |
| Package | 208-pin RQFP (RC208) |
| Programming Technology | EEPROM (in-system programmable) |
| Program/Erase Cycles | 100 minimum |
| JTAG (IEEE 1149.1) Support | Yes |
| Architecture | Third-generation MAX (AND-OR PLA) |
| Mounting Type | Surface Mount |
EPM9560RC208-17 Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell-driven) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | GND β Ground |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | VCC β 5V supply |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | VCC β 5V supply |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | GND β Ground |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | VCC β 5V supply |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | GND β Ground |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | VCC β 5V supply |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | GND β Ground |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | VCC β 5V supply |
| Pin 41 | GCLK1 β Global clock input 1 |
| Pin 42 | GCLK2 β Global clock input 2 |
| Pin 43 | OE1 β Output enable 1 |
| Pin 44 | OE2 β Output enable 2 |
| Pin 45 | CLR β Global clear |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | GND β Ground |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | VCC β 5V supply |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | GND β Ground |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | VCC β 5V supply |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | GND β Ground |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | VCC β 5V supply |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | GND β Ground |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | VCC β 5V supply |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | GND β Ground |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
| Pin 85 | VCC β 5V supply |
| Pin 86 | I/O β User I/O pin |
| Pin 87 | I/O β User I/O pin |
| Pin 88 | GND β Ground |
| Pin 89 | I/O β User I/O pin |
| Pin 90 | I/O β User I/O pin |
| Pin 91 | I/O β User I/O pin |
| Pin 92 | I/O β User I/O pin |
| Pin 93 | VCC β 5V supply |
| Pin 94 | I/O β User I/O pin |
| Pin 95 | I/O β User I/O pin |
| Pin 96 | GND β Ground |
| Pin 97 | I/O β User I/O pin |
| Pin 98 | I/O β User I/O pin |
| Pin 99 | I/O β User I/O pin |
| Pin 100 | I/O β User I/O pin |
| Pin 101 | VCC β 5V supply |
| Pin 102 | I/O β User I/O pin |
| Pin 103 | I/O β User I/O pin |
| Pin 104 | GND β Ground |
| Pin 105 | I/O β User I/O pin |
| Pin 106 | I/O β User I/O pin |
| Pin 107 | I/O β User I/O pin |
| Pin 108 | I/O β User I/O pin |
| Pin 109 | VCC β 5V supply |
| Pin 110 | I/O β User I/O pin |
| Pin 111 | I/O β User I/O pin |
| Pin 112 | GND β Ground |
| Pin 113 | I/O β User I/O pin |
| Pin 114 | I/O β User I/O pin |
| Pin 115 | I/O β User I/O pin |
| Pin 116 | I/O β User I/O pin |
| Pin 117 | VCC β 5V supply |
| Pin 118 | I/O β User I/O pin |
| Pin 119 | I/O β User I/O pin |
| Pin 120 | GND β Ground |
| Pin 121 | I/O β User I/O pin |
| Pin 122 | I/O β User I/O pin |
| Pin 123 | I/O β User I/O pin |
| Pin 124 | I/O β User I/O pin |
| Pin 125 | VCC β 5V supply |
| Pin 126 | I/O β User I/O pin |
| Pin 127 | I/O β User I/O pin |
| Pin 128 | GND β Ground |
| Pin 129 | I/O β User I/O pin |
| Pin 130 | I/O β User I/O pin |
| Pin 131 | I/O β User I/O pin |
| Pin 132 | I/O β User I/O pin |
| Pin 133 | VCC β 5V supply |
| Pin 134 | I/O β User I/O pin |
| Pin 135 | I/O β User I/O pin |
| Pin 136 | GND β Ground |
| Pin 137 | I/O β User I/O pin |
| Pin 138 | I/O β User I/O pin |
| Pin 139 | I/O β User I/O pin |
| Pin 140 | I/O β User I/O pin |
| Pin 141 | VCC β 5V supply |
| Pin 142 | I/O β User I/O pin |
| Pin 143 | I/O β User I/O pin |
| Pin 144 | GND β Ground |
| Pin 145 | I/O β User I/O pin |
| Pin 146 | I/O β User I/O pin |
| Pin 147 | I/O β User I/O pin |
| Pin 148 | I/O β User I/O pin |
| Pin 149 | VCC β 5V supply |
| Pin 150 | I/O β User I/O pin |
| Pin 151 | I/O β User I/O pin |
| Pin 152 | GND β Ground |
| Pin 153 | I/O β User I/O pin |
| Pin 154 | I/O β User I/O pin |
| Pin 155 | I/O β User I/O pin |
| Pin 156 | I/O β User I/O pin |
| Pin 157 | VCC β 5V supply |
| Pin 158 | I/O β User I/O pin |
| Pin 159 | I/O β User I/O pin |
| Pin 160 | GND β Ground |
| Pin 161 | I/O β User I/O pin |
| Pin 162 | I/O β User I/O pin |
| Pin 163 | I/O β User I/O pin |
| Pin 164 | I/O β User I/O pin |
| Pin 165 | VCC β 5V supply |
| Pin 166 | I/O β User I/O pin |
| Pin 167 | I/O β User I/O pin |
| Pin 168 | GND β Ground |
| Pin 169 | I/O β User I/O pin |
| Pin 170 | I/O β User I/O pin |
| Pin 171 | I/O β User I/O pin |
| Pin 172 | I/O β User I/O pin |
| Pin 173 | VCC β 5V supply |
| Pin 174 | I/O β User I/O pin |
| Pin 175 | I/O β User I/O pin |
| Pin 176 | GND β Ground |
| Pin 177 | I/O β User I/O pin |
| Pin 178 | I/O β User I/O pin |
| Pin 179 | I/O β User I/O pin |
| Pin 180 | I/O β User I/O pin |
| Pin 181 | TDI β JTAG test data in |
| Pin 182 | TMS β JTAG test mode select |
| Pin 183 | TCK β JTAG test clock |
| Pin 184 | TDO β JTAG test data out |
| Pin 185 | I/O β User I/O pin |
| Pin 186 | I/O β User I/O pin |
| Pin 187 | I/O β User I/O pin |
| Pin 188 | I/O β User I/O pin |
| Pin 189 | VCC β 5V supply |
| Pin 190 | I/O β User I/O pin |
| Pin 191 | I/O β User I/O pin |
| Pin 192 | GND β Ground |
| Pin 193 | I/O β User I/O pin |
| Pin 194 | I/O β User I/O pin |
| Pin 195 | I/O β User I/O pin |
| Pin 196 | I/O β User I/O pin |
| Pin 197 | VCC β 5V supply |
| Pin 198 | I/O β User I/O pin |
| Pin 199 | I/O β User I/O pin |
| Pin 200 | GND β Ground |
| Pin 201 | I/O β User I/O pin |
| Pin 202 | I/O β User I/O pin |
| Pin 203 | I/O β User I/O pin |
| Pin 204 | I/O β User I/O pin |
| Pin 205 | VCC β 5V supply |
| Pin 206 | I/O β User I/O pin |
| Pin 207 | I/O β User I/O pin |
| Pin 208 | GND β Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC208-17 is suitable for 7 applications: 5V Industrial Glue Logic, Microprocessor Bus Address Decoding, Legacy Peripheral Interfacing (VME / ISA / PCI-derivative), State-Machine and Control Logic, Pin-Compatible Replacement for Legacy MAX 9000 Designs, DSP / Data Acquisition Subsystem Support, Telecom Backplane Control.
5V Industrial Glue Logic
The EPM9560RC208-17 is well suited to 5V industrial glue-logic consolidation, where it can replace multiple discrete 74LS/74HC logic ICs with a single programmable device. Its 560 macro cells and 212 user I/Os easily accommodate 30 to 50 SSI/MSI logic functions, while the deterministic 17 ns pin-to-pin delay guarantees critical timing for handshaking and arbitration paths. Designers route legacy 5V control signals into the 208-pin RQFP and implement the logic in Altera MAX+PLUS II or Quartus II. Compared to FPGA-based replacements, the MAX 9000 family offers instant-on behavior because the configuration is stored in on-chip EEPROM, eliminating external boot memory and reducing BOM cost.
Recommended
Microprocessor Bus Address Decoding
The EPM9560RC208-17 is widely used to decode the address bus of 16-bit and 32-bit microprocessors such as the 80C186, 68SEC000, or MIPS-style CPUs, generating chip-select and wait-state signals for memory banks and peripherals. With 560 macro cells, designers can implement full address-decode trees, interrupt controllers, and bus-arbiter logic in a single CPLD. The 212 I/O pins on the 208-pin RQFP package comfortably support 24-bit address buses plus 16-bit data buses plus control signals. The 17 ns tPD provides adequate margin for 25 MHz 80C186 designs and slower MPUs, while the EE-based configuration ensures deterministic behavior from power-on.
Recommended
Legacy Peripheral Interfacing (VME / ISA / PCI-derivative)
The EPM9560RC208-17 is used to bridge legacy peripheral interfaces such as VMEbus, ISA, and CompactPCI-derivative buses in mature industrial and telecom equipment. Its 560 macro cells implement bus-state machines, parity generators, and timing-control logic, while 212 I/O pins handle the wide parallel buses typical of these architectures. The 17 ns speed grade is well-matched to 8 MHz ISA and 16-bit VME transfers. The in-system JTAG programming interface allows field firmware updates without removing the CPLD from the board, an essential feature for sustaining engineering of installed telecom and factory-automation systems.
Recommended
State-Machine and Control Logic
The EPM9560RC208-17 supports large multi-state control machines for industrial controllers, motor drives, and instrumentation front-ends. The 16 LABs and continuous routing fabric of the MAX architecture mean that 20 to 30 state variables can be implemented without routing congestion or speed degradation. Designers appreciate the 17 ns tPD consistency: state-to-state transitions take the same time regardless of the number of macro cells used, simplifying worst-case timing analysis. The 5V VCC core and 208-pin RQFP package make it thermally robust for enclosed industrial enclosures where junction temperatures can rise substantially.
Recommended
Pin-Compatible Replacement for Legacy MAX 9000 Designs
The EPM9560RC208-17 serves as a sustaining-engineering replacement for legacy MAX 9000 designs whose original CPLDs have failed or become scarce. Because all EPM9560RC208 speed grades share the same 208-pin RQFP footprint, identical pinout, and 5V supply, this part drops into boards originally designed for the -15 or -20 grade without any PCB rework. Engineers should verify the timing budget against the original speed grade: the -17 grade is between -15 and -20, making it a near-universal substitute. The Altera/Intel MAX 9000 family is supported by Quartus II legacy versions and ByteBlaster/USB-Blaster JTAG programmers for in-system reprogramming.
Recommended
DSP / Data Acquisition Subsystem Support
The EPM9560RC208-17 is used in DSP and data-acquisition subsystems to generate timing, address sequencing, and FIFO control signals. With 560 macro cells, it can implement address generators, dual-port RAM controllers, and trigger logic for multi-channel ADC systems. The 117.6 MHz maximum counter frequency supports sample-rate generators for audio and industrial data acquisition, while the 212 user I/Os accommodate wide parallel data buses from ADCs such as the AD976 or AD9220 family. The 5V I/O capability is useful when interfacing to legacy bipolar signal-conditioning chains that produce signals above 3.3V CMOS levels.
Recommended
Telecom Backplane Control
The EPM9560RC208-17 is deployed in legacy telecom backplane controllers where it implements H.110 CT-bus clocks, TDM bus arbiters, and shelf-management logic. Its 212 I/Os comfortably support the multi-drop backplane connectors used in legacy ATCA and proprietary telecom shelves. The 17 ns tPD provides deterministic latency for time-division-multiplexed frame alignment, while the EEPROM-based configuration ensures the backplane controller is operational within microseconds of power-up - critical for hot-swap and shelf-replacement scenarios. The 208-pin RQFP package is well established in legacy telecom form factors, enabling direct board replacement.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC208-17 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-15 | EPM9560RC208-20 | EPM9560RC208-12 | EPM9560RC208-15N | EPM9560RC208-16 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Pin-to-Pin Delay (tPD) | 17 ns | 15 ns (-12%) | 20 ns (+18%) | 12 ns (-29%) | 15 ns (-12%) | 16 ns (-6%) |
| Maximum Counter Frequency | 117.6 MHz | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Macro Cells | 560 | 560 | 560 | 560 | 560 | 560 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Programming Technology | EEPROM (in-system) | EEPROM (in-system) | EEPROM (in-system) | EEPROM (in-system) | EEPROM (in-system) | EEPROM (in-system) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
| Unit Price (qty 1) | USD 95.00 | USD 80.00 (approx) | USD 105.00 (approx) | USD 125.00 (approx) | USD 82.00 (approx) | USD 88.00 (approx) |
Key Differentiators
- Mid-range speed grade in mature MAX 9000 family (vs EPM9560RC208-15)
- 212 user I/O pins in legacy 5V architecture (vs EPM9480RC208-15)
- 5V VCC core with multi-voltage I/O bank support (vs EPM7256SRC208-10)
Design Notes
The EPM9560RC208-17 requires a stable 5V VCC supply with decoupling capacitors placed as close as possible to every VCC/GND pin pair. Use one 0.1 uF ceramic and one 10 uF tantalum per VCC pin, plus a single 100 uF bulk capacitor at the board entry point. According to the MAX 9000 datasheet, VCC rise time must be monotonic and under 100 ms to ensure proper power-on reset of the EEPROM-based configuration logic. Add a supervisory reset IC if the 5V rail has slow rise or significant noise during hot-plug events.
Estimated: At 5V VCC, all 212 I/Os switching at 10 MHz with 50 pF loads, the EPM9560RC208-17 in the 208-pin RQFP package dissipates approximately 1.5 to 2.0 W. The RQFP has a typical theta_JA of around 35 C/W in still air, leading to a junction-temperature rise of 53 to 70 C above ambient. In enclosed industrial enclosures, add forced-air cooling or thermal vias under the package thermal pad region to keep Tj below 100 C for reliable long-term operation.
Place the EPM9560RC208-17 with all decoupling capacitors on the same PCB layer, using wide power planes for VCC and a continuous ground plane for GND. Route high-speed clock signals (GCLK1, GCLK2) with controlled impedance and matched lengths to minimize skew. Keep JTAG signals (TDI, TMS, TCK, TDO) away from switching outputs to avoid noise coupling during in-system programming. The 208-pin RQFP package has a 0.5 mm pitch - follow standard fine-pitch QFP PCB design rules for land pattern and solder mask.
Do not confuse the EPM9560RC208-17 with the EPM9560ARC208-10: the A-suffix is the Altera (Intel) re-marked version, while RC denotes the original package code. Confirm the exact ordering code with the Altera/Intel part-number decoder before sourcing. Also note that the -17 speed grade is sometimes abbreviated as '17' without the dash in distributor part search tools; explicitly request 'RC208-17' when ordering to avoid receiving the wrong speed grade.
The MAX 9000 family I/O drivers have TTL-compatible thresholds but limited slew-rate control. For signals longer than 50 mm or with stubs, add 22 to 33 ohm series-termination resistors close to the EPM9560RC208-17 output pin to dampen reflections. For clock outputs, prefer using one of the two global clock (GCLK) pins rather than routing an internal signal as a clock, because GCLK paths have lower skew and tighter jitter than the PIA routing fabric.
Compliance Information
Compliance information for EPM9560 family is not present in the verified web data; engineers should request the latest material declaration from Intel/Altera legacy product support before specifying this part in new designs.
