EPM9560RC208-3 - 560 Macrocell MAX 9000 EPLD | Intel / Altera
MPN: EPM9560RC208-3 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $85.5 | $855.00 |
| 100 | $72 | $7,200.00 |
| 500 | $64 | $32,000.00 |
| 1,000 | $58.5 | $58,500.00 |
Drop-in alternatives for EPM9560RC208-3 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RC208-10
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$15.4 / Unit
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View Datasheet βEPM9560RC208-20
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View Datasheet βEPM9560RC208-12
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View Datasheet βEPM9560RC208-17
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$54.75 / Unit
View Datasheet βEPM9560RC208-3 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 16 |
| Usable Gates | 12,000 |
| Pin-to-Pin Delay (speed grade -3) | approximately 3 ns (slowest grade) |
| Speed Grade | -3 |
| Package | 208-pin RQFP (Power Quad Flat Pack) |
| I/O Voltage Tolerance | 5V |
| Process Technology | 0.5 Β΅m CMOS EPROM |
| Programming Interface | ByteBlaster / BitBlaster (JTAG-compatible) |
| Lifecycle | Mature / Last-time-buy (per Altera PDN for selected MAX 9000 ordering codes) |
EPM9560RC208-3 Pin Configuration
| Pin 1 | I/O β User I/O pin (function defined by user design) |
| Pin 2 | I/O β User I/O pin |
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| Pin 9 | GND β Ground |
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| Pin 52 | I/O β User I/O pin |
| Pin 53 | VCC β Supply voltage (5V) |
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| Pin 81 | GND β Ground |
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| Pin 106 | I/O β User I/O pin |
| Pin 107 | VCC β Supply voltage (5V) |
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| Pin 135 | GND β Ground |
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| Pin 160 | I/O β User I/O pin |
| Pin 161 | VCC β Supply voltage (5V) |
| Pin 162 | I/O β User I/O pin |
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| Pin 189 | GND β Ground |
| Pin 190 | I/O β User I/O pin |
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| Pin 202 | I/O β User I/O pin |
| Pin 203 | TDI β JTAG Test Data In |
| Pin 204 | TMS β JTAG Test Mode Select |
| Pin 205 | TCK β JTAG Test Clock |
| Pin 206 | TDO β JTAG Test Data Out |
| Pin 207 | I/O β User I/O pin (global clock option) |
| Pin 208 | I/O β User I/O pin (global clock option) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC208-3 is suitable for 6 applications: Telecommunications Line-Card Glue Logic, Industrial Control Board Logic Consolidation, Legacy ISA / VME / PCI Bus Bridges, Military / Aerospace Ruggedized Systems, Test & Measurement Instrumentation, Printer / Plotter / Imaging Controller Boards.
Telecommunications Line-Card Glue Logic
The EPM9560RC208-3 is well suited to telecommunications line-card glue-logic consolidation because of its 560 macrocells, 12,000 usable gates, and 5V-tolerant I/O. The MAX 9000 architecture's deterministic timing model maps directly to legacy TDM bus decoding, address-mapping, and backplane-interface state machines commonly found in central-office equipment. With 16 LABs interconnected by the global PIA, designers can integrate multiple 22V10-equivalent functions into a single device. The 208-pin RQFP footprint provides ample I/O for parallel backplane interfaces, while the EPROM-based non-volatile configuration eliminates external boot memory. The -3 speed grade is appropriate where timing margins exceed 30 ns, typical of legacy telecom backplanes.
Recommended
Industrial Control Board Logic Consolidation
Industrial PLC and process-control boards benefit from the EPM9560RC208-3's combination of high macrocell count, 5V-tolerant I/O, and deterministic tpd timing. Engineers routinely replace 8 to 12 discrete 22V10 / GAL22V10 / PALCE devices with a single MAX 9000 device, simplifying BOM, lowering board area, and improving noise immunity. The 208-pin RQFP package is well matched to legacy through-hole-friendly industrial layouts and supports 5V interfaces directly without level shifters. The -3 speed grade suits scan-rate-limited control loops and HMI bus interfaces. Long-term industrial deployments value the EPROM non-volatile configuration for field serviceability.
Recommended
Legacy ISA / VME / PCI Bus Bridges
The EPM9560RC208-3 was a workhorse for legacy ISA, VME, and 5V PCI bus-bridge designs in the 1990s and 2000s, and many such designs remain in service today. Its 560 macrocells and 160+ user I/O pins comfortably implement address decoding, bus arbitration, wait-state generation, and interrupt steering for 8/16/32-bit parallel buses. The 5V-tolerant I/O matches legacy bus signaling levels without external transceivers, while the deterministic pin-to-pin delay of the MAX 9000 architecture simplifies worst-case timing analysis for asynchronous handshakes. The 208-pin RQFP package is pin-compatible across the EPM9560RC208 speed-grade family, allowing easy migration from -3 to -10 or -20 if timing closure becomes an issue.
Recommended
Military / Aerospace Ruggedized Systems
Ruggedized military and aerospace subsystems that still require 5V-tolerant, non-volatile programmable logic often specify the EPM9560 family because of its mature supply chain, proven EPROM-based configuration, and high I/O count. The 208-pin RQFP package supports conformal coating and is widely accepted in MIL-STD-454 and similar ruggedization programs. The -3 grade's slower edge rates are actually advantageous in radiation-tolerant and EMI-sensitive environments. The deterministic MAX 9000 timing model is documented and stable, which is important for systems that must demonstrate bit-for-bit reproducibility across long production runs.
Recommended
Test & Measurement Instrumentation
Test-and-measurement instruments such as logic analyzers, protocol testers, and ATE fixture controllers integrate the EPM9560RC208-3 to consolidate address decoding, channel multiplexing, and timing-control logic. The 560 macrocells and 12,000 usable gates can absorb what would otherwise require a dozen PAL/GAL devices, while the 5V-tolerant I/O interfaces directly to legacy instrumentation buses. The -3 speed grade is sufficient for sub-50 MHz control planes, which dominate bench-top and rack-mount instruments. The 208-pin RQFP footprint allows straightforward rework and field replacement, important for long-life test equipment deployed at customer sites.
Recommended
Printer / Plotter / Imaging Controller Boards
Large-format printers, plotters, and imaging controllers historically used the EPM9560RC208-3 for high-density glue logic, including motor-control state machines, sensor-multiplexer decoding, and parallel image-data-path arbitration. The 560 macrocells and 208-pin RQFP package support the many parallel interfaces (Centronics, SCSI, custom backplanes) typical of imaging systems. 5V-tolerant I/O directly interfaces to legacy motor-driver and sensor front-ends without level shifting. The deterministic MAX 9000 timing simplifies design verification for safety-critical paper-path interlocks. The -3 speed grade is sufficient for stepper-motor sequencing and image-data buffering at typical print-engine data rates.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC208-3 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-10 | EPM9560RC208-15 | EPM9560RC208-20 | EPM9560RC208-12 | EPM9560RC208-17 |
|---|---|---|---|---|---|---|
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Package | 208-pin RQFP | 208-pin RQFP (same) | 208-pin RQFP (same) | 208-pin RQFP (same) | 208-pin RQFP (same) | 208-pin RQFP (same) |
| Speed Grade | -3 (slowest commercial) | -10 | -15 | -20 (fastest) | -12 | -17 |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| Logic Array Blocks (LABs) | 16 | 16 | 16 | 16 | 16 | 16 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Pin-to-Pin Delay (tpd) | ~3 ns (slowest grade) | ~10 ns | ~15 ns | ~20 ns | ~12 ns | ~17 ns |
| I/O Voltage Tolerance | 5V | 5V | 5V | 5V | 5V | 5V |
Key Differentiators
- Slowest commercial speed grade in the MAX 9000 family (vs EPM9560RC208-20)
- Largest density member of the classic MAX 9000 EPLD family (vs EPM9320RC208-20)
- 5V-tolerant I/O for legacy bus compatibility (vs Modern MAX V / MAX 10 CPLDs)
Design Notes
Estimated: The EPM9560RC208-3 is in mature / last-time-buy lifecycle per Altera's PDN for selected MAX 9000 ordering codes. Before committing to a new production run, confirm remaining inventory with franchised distributors (Jotrin, Veswin, VEKEMO, DigiKey base product page) and verify that the 208-pin RQFP finish is compatible with your RoHS / lead-free process. Do not assume new Altera fab output for this part beyond the PDN horizon.
The 208-pin RQFP package dissipates modest power (typical Icc under 200 mA at 5V for MAX 9000 EPLDs) but still requires thermal relief on inner power and ground pins. Use a multi-layer PCB with dedicated VCC/GND planes and stitch multiple ground pins (9, 81, 135, 189) together with low-impedance vias to the ground plane. Conformal coating in ruggedized applications traps heat and should be evaluated against the part's thermal envelope.
Place the ByteBlaster / BitBlaster JTAG header within 100 mm of the EPM9560RC208-3's TDI/TMS/TCK/TDO pins (203-206) for reliable in-system programming. Keep JTAG traces short and isolated from high-speed switching signals to avoid programming errors. Decouple VCC pins (53, 107, 161) with 0.1 Β΅F ceramic capacitors placed within 3 mm of each pin, plus a bulk 10 Β΅F tantalum or ceramic capacitor nearby.
Estimated: The -3 speed grade is the slowest commercial grade in the MAX 9000 family, so worst-case tpd may exceed 30 ns under all temperature and voltage corners. Run static timing analysis under industrial temperature (125 Β°C) and minimum VCC (4.75 V) corners in MAX+PLUS II or Quartus to confirm timing closure. If your design needs more margin, drop in the same-package -10, -15, or -20 grade without PCB rework.
Estimated: At 5V supply with all 560 macrocells active, the EPM9560RC208-3 typically draws 150-200 mA Icc; quiescent current drops to a few milliamps when the device is idle but still configured. Use a 5V regulator with at least 500 mA headroom to accommodate in-rush during EPROM-based configuration. Add a power-good signal or reset delay to hold downstream logic in reset until configuration completes.
Compliance Information
RoHS / lead-free status marked [DATA_NEEDED] because the verified web data does not contain a current compliance certificate for the EPM9560RC208-3. The mature MAX 9000 family historically used tin-lead finish; for RoHS-critical applications request a formal certificate from the seller or migrate to MAX V / MAX 10.
