EPM9560RC208-7N vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560RC208-7N by Intel and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RC208-7N - MAX 9000 EPLD, 208-Pin RQFP, 7ns | Intel (Altera)
EPM9560RC208-7N β Last Time Buy
Specification Comparison
| Parameter | EPM9560RC208-7N | EPM9560RC208-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $58.00 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Device | EPM9560 | β |
| Logic Elements / Macrocells | [DATA_NEEDED: macrocell count] | β |
| Usable Gates | [DATA_NEEDED: usable gate count] | 12,000 gates |
| Propagation Delay (tPD) | 7 ns (speed grade -7) | β |
| Package | RQFP-208 (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Pin Count | 208 | β |
| User I/O | [DATA_NEEDED: user I/O count] | β |
| Process Technology | 0.65 micron CMOS EEPROM | β |
| Programmability | In-system / EEPROM-based | β |
| Supply Voltage | 5 V (VCC, typical for MAX 9000) | 5.0 V |
| Operating Temperature | [DATA_NEEDED: commercial or industrial grade] | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Compliant (Pb-free, N suffix) | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes (N suffix) | β |
| Manufacturer | Intel (formerly Altera) | β |
| Device Type | β | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | β | 560 macro cells |
| Pin-to-Pin Delay | β | 15 ns |
| Counter Speed | β | 117.6 MHz |
| Configuration Technology | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | β | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | β | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | β | -15 (15 ns pin-to-pin) |
| Architecture | β | Third-generation Multiple Array MatriX (MAX) |