EPM9560RC208-7N vs EPM9560RC208-15 Comparison

Detailed side-by-side comparison of EPM9560RC208-7N by Intel and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC208-7N EPM9560RC208-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy Obsolete
Family MAX 9000 MAX 9000
Device EPM9560 —
Logic Elements / Macrocells [DATA_NEEDED: macrocell count] —
Usable Gates [DATA_NEEDED: usable gate count] 12,000 gates
Propagation Delay (tPD) 7 ns (speed grade -7) —
Package RQFP-208 (Power Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
Pin Count 208 —
User I/O [DATA_NEEDED: user I/O count] —
Process Technology 0.65 micron CMOS EEPROM —
Programmability In-system / EEPROM-based —
Supply Voltage 5 V (VCC, typical for MAX 9000) 5.0 V
Operating Temperature [DATA_NEEDED: commercial or industrial grade] [DATA_NEEDED: operating temperature range]
Mounting Type Surface Mount Surface Mount
RoHS Status Compliant (Pb-free, N suffix) [DATA_NEEDED: RoHS status]
Lead-Free Yes (N suffix) —
Manufacturer Intel (formerly Altera) —
Device Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Macro Cells — 560 macro cells
Pin-to-Pin Delay — 15 ns
Counter Speed — 117.6 MHz
Configuration Technology — EEPROM (non-volatile)
In-System Programmability — Yes, via IEEE Std. 1149.1 JTAG
Number of I/O Pins — [DATA_NEEDED: number of I/O pins]
Logic Array Blocks — [DATA_NEEDED: number of logic array blocks]
Speed Grade — -15 (15 ns pin-to-pin)
Architecture — Third-generation Multiple Array MatriX (MAX)

Datasheets & Resources

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