EPM9560RC208-7N vs EPM9560RC208-15 Comparação
Comparação detalhada lado a lado de EPM9560RC208-7N por Intel e EPM9560RC208-15 por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Intel
EPM9560RC208-7N - MAX 9000 EPLD, 208-Pin RQFP, 7ns | Intel (Altera)
EPM9560RC208-7N ⚠ Última compra
Comparação de especificações
| Parâmetro | EPM9560RC208-7N | EPM9560RC208-15 |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Última compra | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $58,00 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Device | EPM9560 | — |
| Logic Elements / Macrocells | [DATA_NEEDED: macrocell count] | — |
| Usable Gates | [DATA_NEEDED: usable gate count] | 12,000 gates |
| Propagation Delay (tPD) | 7 ns (speed grade -7) | — |
| Encapsulamento | RQFP-208 (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Contagem de pinos | 208 | — |
| User I/O | [DATA_NEEDED: user I/O count] | — |
| Process Technology | 0.65 micron CMOS EEPROM | — |
| Programmability | In-system / EEPROM-based | — |
| Tensão de alimentação | 5 V (VCC, typical for MAX 9000) | 5.0 V |
| Temperatura de operação | [DATA_NEEDED: commercial or industrial grade] | [DATA_NEEDED: operating temperature range] |
| Tipo de montagem | Surface Mount | Surface Mount |
| Status RoHS | Compliant (Pb-free, N suffix) | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes (N suffix) | — |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |