EPM9560RC208-7N vs EPM9560RC208-15 Vergleich
Detaillierter Direktvergleich von EPM9560RC208-7N von Intel und EPM9560RC208-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM9560RC208-7N - MAX 9000 EPLD, 208-Pin RQFP, 7ns | Intel (Altera)
EPM9560RC208-7N ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EPM9560RC208-7N | EPM9560RC208-15 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $58,00 | $0,00 |
| Family | MAX 9000 | MAX 9000 |
| Device | EPM9560 | — |
| Logic Elements / Macrocells | [DATA_NEEDED: macrocell count] | — |
| Usable Gates | [DATA_NEEDED: usable gate count] | 12,000 gates |
| Propagation Delay (tPD) | 7 ns (speed grade -7) | — |
| Gehäuse | RQFP-208 (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Pin-Anzahl | 208 | — |
| User I/O | [DATA_NEEDED: user I/O count] | — |
| Process Technology | 0.65 micron CMOS EEPROM | — |
| Programmability | In-system / EEPROM-based | — |
| Versorgungsspannung | 5 V (VCC, typical for MAX 9000) | 5.0 V |
| Betriebstemperatur | [DATA_NEEDED: commercial or industrial grade] | [DATA_NEEDED: operating temperature range] |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | Compliant (Pb-free, N suffix) | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes (N suffix) | — |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |