EPM9560RC208-7N vs EPM9560RC208-15 对比

详细并排对比 EPM9560RC208-7N 出自 Intel 和 EPM9560RC208-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Intel
EPM9560RC208-7N EPM9560RC208-7N - MAX 9000 EPLD, 208-Pin RQFP, 7ns | Intel (Altera)

EPM9560RC208-7N - MAX 9000 EPLD, 208-Pin RQFP, 7ns | Intel (Altera)

EPM9560RC208-7N ⚠ 最后一次采购

规格对比

参数 EPM9560RC208-7N EPM9560RC208-15
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $58.00 $0.00
Family MAX 9000 MAX 9000
Device EPM9560 —
Logic Elements / Macrocells [DATA_NEEDED: macrocell count] —
Usable Gates [DATA_NEEDED: usable gate count] 12,000 gates
Propagation Delay (tPD) 7 ns (speed grade -7) —
封装 RQFP-208 (Power Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
引脚数量 208 —
User I/O [DATA_NEEDED: user I/O count] —
Process Technology 0.65 micron CMOS EEPROM —
Programmability In-system / EEPROM-based —
电源电压 5 V (VCC, typical for MAX 9000) 5.0 V
工作温度 [DATA_NEEDED: commercial or industrial grade] [DATA_NEEDED: operating temperature range]
安装类型 Surface Mount Surface Mount
RoHS 状态 Compliant (Pb-free, N suffix) [DATA_NEEDED: RoHS status]
Lead-Free Yes (N suffix) —
Manufacturer Intel (formerly Altera) —
Device Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Macro Cells — 560 macro cells
Pin-to-Pin Delay — 15 ns
Counter Speed — 117.6 MHz
Configuration Technology — EEPROM (non-volatile)
In-System Programmability — Yes, via IEEE Std. 1149.1 JTAG
Number of I/O Pins — [DATA_NEEDED: number of I/O pins]
Logic Array Blocks — [DATA_NEEDED: number of logic array blocks]
Speed Grade — -15 (15 ns pin-to-pin)
Architecture — Third-generation Multiple Array MatriX (MAX)

数据手册与资源

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