EPM9560RC208-9 vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560RC208-9 by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-9 | EPM9560RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD / EPLD | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 212 | — |
| Pin-to-Pin Delay (tPD) | 9 ns | — |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX from datasheet] | — |
| Core Voltage | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Programmability | In-system programmable (JTAG) | — |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Speed Grade | -9 | -15 (15 ns pin-to-pin) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Process Technology | EPROM-based (one-time programmable) / UV-erasable | — |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Supply Voltage | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |