EPM9560RC208-9 vs EPM9560RC208-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-9 sa pamamagitan ng Altera at EPM9560RC208-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC208-9 | EPM9560RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD / EPLD | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 212 | — |
| Pin-to-Pin Delay (tPD) | 9 ns | — |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX from datasheet] | — |
| Core Voltage | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Programmability | In-system programmable (JTAG) | — |
| Packhaging | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Speed Grade | -9 | -15 (15 ns pin-to-pin) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Process Technology | EPROM-based (one-time programmable) / UV-erasable | — |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Volte ng Pagbibigay | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |