EPM9560RC240-15C vs EPM9560ARC240-10N Comparison
Detailed side-by-side comparison of EPM9560RC240-15C by Intel and EPM9560ARC240-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560ARC240-10N - MAX 9000 CPLD 560 Macro 191 IOs | Altera/Intel
EPM9560ARC240-10N ObsoleteSpecification Comparison
| Parameter | EPM9560RC240-15C | EPM9560ARC240-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based CPLD | — |
| Usable Gates | 12,000 | — |
| Macrocells | 560 | — |
| Logic Array Blocks | 20 | — |
| User I/O Pins | 187 | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Propagation Delay (tPD) | 15 ns | 10 ns |
| Supply Voltage | 5.0 V | — |
| Operating Voltage Range | 3.3 V or 5 V | — |
| Package | 240-pin RQFP (PowerQuad II) | 240-pin RQFP (32x32 mm) |
| Terminal Pitch | 0.5 mm | — |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (Commercial) | 0°C to +70°C (Commercial) |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (ISP via JTAG) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan | — |
| Process Technology | CMOS | CMOS EEPROM |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-RoHS (legacy Altera part) |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| Logic Family | — | MAX 9000 (CPLD) |
| Macro Cells | — | 560 |
| User I/Os | — | 191 |
| Logic Array Blocks (LABs) | — | 16 |
| Internal Frequency (fMAX) | — | 145 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Programming Interface | — | IEEE 1149.1 JTAG / ByteBlaster |
| Programmability | — | In-system, EEPROM-based (non-volatile) |
| I/O Standard | — | 5.0 V TTL-compatible |