EPM9560RC240-15C - MAX 9000 CPLD 560 Macro Cells | Intel
MPN: EPM9560RC240-15C ✗ End of Life| Qty | Unit Price | Extended |
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Drop-in alternatives for EPM9560RC240-15C — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RC240-15
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View Datasheet →EPM9560RC240-10N
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View Datasheet →EPM9560RC240-15C Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | EEPROM-based CPLD |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| Logic Array Blocks | 20 |
| User I/O Pins | 187 |
| Maximum Internal Frequency | 117.6 MHz |
| Propagation Delay (tPD) | 15 ns |
| Supply Voltage | 5.0 V |
| Operating Voltage Range | 3.3 V or 5 V |
| Package | 240-pin RQFP (PowerQuad II) |
| Terminal Pitch | 0.5 mm |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (Commercial) |
| Configuration Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes (ISP via JTAG) |
| JTAG Interface | IEEE 1149.1 boundary-scan |
| Process Technology | CMOS |
EPM9560RC240-15C 240-pin rqfp (powerquad ii) Pin Configuration Guide
Complete pinout information for EPM9560RC240-15C (240-pin rqfp (powerquad ii) package) with 187 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC240-15C.
Refer to the datasheet for full pin configuration.
Estimated pin count: 187 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC240-15C is suitable for 6 applications: PCI Bus Bridging and Interfacing, Industrial Control Backplane Logic, Telecommunications Line Card Glue Logic, Legacy System Maintenance and Repair, High-Speed Address Decoding and DMA Control, Prototyping and Educational Logic Design.
PCI Bus Bridging and Interfacing
The EPM9560RC240-15C is well suited to PCI bus bridging because its 187 user I/O pins and 560 macrocells can implement the address/data multiplexing, parity generation, and target/initiator state machines required by the PCI Local Bus specification. With a 117.6 MHz maximum internal frequency and 15 ns pin-to-pin delay, the device meets the 33 MHz PCI clock timing budget with margin. Designers typically implement the PCI target interface as a Mealy state machine in the CPLD, using the EEPROM non-volatile configuration to ensure the bridge is active within microseconds of power-up, before the host processor begins PCI enumeration. The 5 V tolerant I/O supports legacy 5 V PCI signaling, while the 240-pin RQFP package provides enough pins for a 32-bit address/data bus plus control signals. A common trade-off is that the MAX 9000 architecture consumes more static power than modern CPLDs, so thermal management should be considered in densely packed line cards.
Recommended
Industrial Control Backplane Logic
In industrial control systems, the EPM9560RC240-15C implements backplane glue logic such as address decoding, chip-select generation, and interrupt arbitration for VME, CompactPCI, and proprietary 5 V backplanes. The 560 macrocells allow multiple bus masters to be arbitrated in a single device, while the 187 I/O pins accommodate wide address and data buses. The EEPROM configuration is a decisive advantage in factory automation: the CPLD is operational immediately at power-up without a configuration PROM, so the control system boots deterministically even after an unplanned power cycle. The 5.0 V supply matches legacy industrial backplane levels, and the 0C to +70C commercial temperature range suits controlled-cabinet environments. Designers should note that the 15 ns propagation delay limits the maximum backplane clock to approximately 66 MHz for combinatorial paths; registered paths can run at the full 117.6 MHz internal frequency. For higher-reliability variants, the industrial-temperature MAX 9000 versions should be evaluated.
Recommended
Telecommunications Line Card Glue Logic
Telecommunications line cards historically used the EPM9560RC240-15C for glue logic between framers, DSPs, and backplane interfaces. The device's 12,000 usable gates and 560 macrocells can implement timeslot interchange control, HDLC channel selection, and clock multiplexing for T1/E1 and SONET/SDH line cards. The 117.6 MHz internal frequency supports the clock rates used in these systems, and the 187 I/O pins allow multiple serial data streams to be routed through a single CPLD. The non-volatile EEPROM configuration is critical in telecom equipment, where line cards must become operational within milliseconds of insertion to avoid dropping calls. The 5 V supply and 5 V tolerant I/O match the legacy telecom backplane environment. A key design consideration is that the MAX 9000 family is obsolete, so new telecom designs should migrate to MAX II or MAX V CPLDs, which offer equivalent logic density at lower power and in smaller packages, though a PCB redesign is required.
Recommended
Legacy System Maintenance and Repair
The EPM9560RC240-15C is widely sourced for maintenance and repair of legacy equipment in aerospace, defense, and industrial sectors where the original MAX 9000 design must be preserved. Because the device is EEPROM-based and non-volatile, replacement parts can be programmed with the original JEDEC file and dropped into the existing socket without any board modification. The 240-pin RQFP package and 187 I/O pins match the original footprint exactly, and the 15 ns speed grade ensures timing compatibility with the original design. Sourcing engineers should verify that replacement parts are genuine and not re-marked counterfeits, as the MAX 9000 family is a common target for counterfeiters. The EPM9560RC240-15 and EPM9560RC240-12 are pin-compatible substitutes that can be used when the -15C grade is unavailable, provided the design is recompiled for the new speed grade.
Recommended
High-Speed Address Decoding and DMA Control
The EPM9560RC240-15C implements high-speed address decoding and DMA control logic in embedded systems where a discrete PAL or GAL is insufficient. With 560 macrocells, the device can decode multiple memory and I/O regions simultaneously, generate wait states, and arbitrate DMA requests between peripherals and the CPU. The 15 ns pin-to-pin propagation delay supports zero-wait-state operation for processors running up to approximately 33 MHz, while registered decode paths can operate at the full 117.6 MHz internal frequency. The 187 I/O pins allow a full 32-bit address bus plus control signals to be decoded in a single device, reducing chip count and board area. The EEPROM configuration ensures the decode logic is active immediately at power-up, which is essential for boot-time memory mapping. Designers should add a 0.1 uF decoupling capacitor per power pin and use a ground plane to minimize switching noise on the high-fanout decode outputs.
Recommended
Prototyping and Educational Logic Design
The EPM9560RC240-15C is used in university laboratories and prototyping environments for teaching programmable logic design, state-machine implementation, and bus interfacing. Its 560 macrocells and 187 I/O pins provide ample resources for complex student projects, while the 5 V supply and through-hole-friendly RQFP footprint simplify breadboard and evaluation-board integration. The IEEE 1149.1 JTAG interface allows in-system programming and boundary-scan testing, giving students hands-on experience with industry-standard configuration and test methods. The MAX+PLUS II development tool supports schematic capture, VHDL, and Verilog entry for the MAX 9000 family. Although the device is obsolete, its widespread availability on the secondary market and its robust 5 V I/O make it a practical teaching platform. Educators should note that modern curricula increasingly favor MAX II or MAX V devices, which offer similar logic density at lower cost and power.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC240-15C — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC240-15 | EPM9560RC240-12 | EPM9560RC240-10 | EPM9560ARC240-10 |
|---|---|---|---|---|---|
| Package | 240-pin RQFP | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Macrocells | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| User I/O Pins | 187 | 187 | 187 | 187 | 187 |
| Propagation Delay | 15 ns | 15 ns | 12 ns | 10 ns | 10 ns |
| Maximum Internal Frequency | 117.6 MHz | 117.6 MHz | 144.9 MHz | 144.9 MHz | 144.9 MHz |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
Key Differentiators
- Highest macrocell count in MAX 9000 family (vs EPM9480RC240-15)
- Non-volatile EEPROM configuration (vs SRAM-based FPGAs)
- 5 V operation and 5 V tolerant I/O (vs EPM9560ARC240-10)
- 187 user I/O pins in a single device (vs EPM9400RC240-15)
Design Notes
The EPM9560RC240-15C requires a stable 5.0 V supply with adequate decoupling. Place a 0.1 uF ceramic capacitor as close as possible to each VCC pin, and add a 10 uF bulk capacitor per power rail. The MAX 9000 family draws significant dynamic current during high-frequency switching; estimate the supply current from the Altera MAX 9000 datasheet power calculator using your design's toggle rates. Estimated: at 117.6 MHz with 50% of macrocells toggling, supply current can exceed 500 mA, so the regulator must be sized accordingly.
The 240-pin RQFP package has a 0.5 mm terminal pitch, requiring fine-line PCB fabrication and careful solder-paste stencil design. Use a stencil thickness of 0.12-0.15 mm and a paste-to-pad ratio that prevents bridging. Provide a solid ground plane under the device to minimize switching noise and improve thermal dissipation. Route high-speed clock and I/O traces with controlled impedance and keep them away from sensitive analog signals. The RQFP heat-spreader should be soldered to a thermal pad connected to ground for heat dissipation.
A common pitfall with the EPM9560RC240-15C is failing to recompile the design when substituting a different speed grade. The -15, -12, and -10 variants have different timing characteristics, and a design compiled for -15 may not meet timing on -10 or vice versa. Always recompile and re-run static timing analysis after any speed-grade change. Additionally, the MAX 9000 family is obsolete; verify that replacement parts are genuine, as counterfeit re-marked devices are common. Program and verify the JEDEC file before soldering, and use the JTAG boundary-scan chain to confirm device identity.
Compliance Information
Compliance information for the EPM9560RC240-15C was not found in the verified web data. The MAX 9000 family predates RoHS and REACH regulations, so compliance status must be verified with the manufacturer or distributor. The 'N' suffix variants (e.g., EPM9560RC240-10N) indicate lead-free construction.
