EPM9560RC240-15YY - MAX 9000 CPLD 560 Macrocells | Intel | 240-RQFP
MPN: EPM9560RC240-15YY ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $86.5 | $865.00 |
| 100 | $78 | $7,800.00 |
| 500 | $70.25 | $35,125.00 |
| 1,000 | $64.5 | $64,500.00 |
Drop-in alternatives for EPM9560RC240-15YY — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RC240-15
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$174.72 / Unit
View Datasheet →EPM9560RC240-15W
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View Datasheet →EPM9560RC240-15N
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View Datasheet →EPM9560RC240-15C
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View Datasheet →EPM9560RC240-12
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$9.95 / Unit
View Datasheet →EPM9560ARC240-10
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View Datasheet →EPM9560RC240-15YY Maximum Ratings & Electrical Characteristics
| Family | MAX 9000A |
| Logic Type | CMOS EEPROM-based CPLD |
| Number of Macrocells | 560 |
| Usable Gates | 12,000 |
| Number of User I/O | 191 |
| Maximum Operating Frequency | 117.6 MHz |
| Propagation Delay (tpd) | 15 ns |
| Supply Voltage (VCC) | 5.0 V |
| Programmability | In-system via IEEE 1149.1 (JTAG) |
| Package Type | RQFP-240 (Plastic Quad Flat Pack) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 C to +70 C (commercial) |
| Speed Grade | -15 |
| RoHS Status | Non-RoHS (YY suffix indicates non-compliant / matte tin or SnPb lead finish per Altera legacy convention) |
EPM9560RC240-15YY rqfp-240 (plastic quad flat pack) Pin Configuration Guide
Complete pinout information for EPM9560RC240-15YY (rqfp-240 (plastic quad flat pack) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC240-15YY.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC240-15YY is suitable for 6 applications: 32-bit Microprocessor Glue Logic, PCI / VME Bus Bridge, Industrial Control State Machine, Peripheral Controller Hub, Address Decoder / Chip-Select Generator, Legacy Telecom Line Card.
32-bit Microprocessor Glue Logic
The EPM9560RC240-15YY is well suited for 32-bit microprocessor glue logic because its 560 macrocells and 191 user I/Os deliver enough capacity to consolidate dozens of 74-series decoder, latch, and bus-driver chips into one CPLD. The deterministic 15 ns pin-to-pin propagation delay matches 50-66 MHz system buses without timing-closure issues, and the JTAG (IEEE 1149.1) interface allows in-system reconfiguration. Place the part between the CPU and memory/peripheral bus to consolidate address decoding, wait-state generation, and chip-select logic; expect 60-70% board-area reduction compared to discrete PAL implementations.
Recommended
PCI / VME Bus Bridge
The EPM9560RC240-15YY serves as a PCI-to-local bus or VME bus bridge because the 191 I/O count and 5 V MultiVolt interface directly drive 32-bit PCI signalling at 33 MHz. Its 560 macrocells hold full PCI target-state machines, parity generation, and interrupt-acknowledge logic in a single device, while the deterministic 15 ns tpd meets PCI 2.1 tVAL timing without wait states. Use the JTAG chain to in-system update bridge firmware; ensure trace impedance of 65 ohms +/- 10% for the PCI segment.
Recommended
Industrial Control State Machine
The EPM9560RC240-15YY is a strong fit for industrial state-machine controllers due to its 560 macrocells supporting 50-100 states with combinational and registered outputs, plus 191 I/Os for sensor and actuator interfacing. The 5 V core and 0-70 C commercial temperature range suit factory-floor cabinets; for harsher environments use the EPM9560RC240-15C industrial-temperature variant. The deterministic 15 ns tpd eliminates race conditions in sequential logic, a key advantage over microcontrollers with interrupt latency.
Recommended
Peripheral Controller Hub
The EPM9560RC240-15YY can replace multiple PAL/GAL devices in peripheral hubs (USB, SCSI, IDE) because its 12,000-gate capacity and 191 I/Os allow channel multiplexing, command decoding, and DMA handshaking in a single chip. The 5 V tolerance on every I/O pin interfaces directly with legacy 5 V peripherals without level shifters. Power consumption is approximately 1.5-2 W at full toggle rate; provide at least 4 layer PCB with dedicated ground plane.
Recommended
Address Decoder / Chip-Select Generator
The EPM9560RC240-15YY excels at large address-decoding tasks (e.g., 32-bit systems needing 20+ chip selects) because each macrocell delivers a product term with up to 36 inputs, far more than discrete 22V10 PALs. The 15 ns tpd means the decoded chip-select arrives well within typical CPU access times. Place the part adjacent to the memory bus to minimize trace delay. The JTAG ISP allows last-minute address-map adjustments without board rework.
Recommended
Legacy Telecom Line Card
The EPM9560RC240-15YY is commonly found in legacy telecom line cards for T1/E1 framers, HDLC controllers, and time-slot interchangers. Its 560 macrocells consolidate framing, alarm, and switching logic that previously required 8-12 discrete PALs, while 5 V tolerance interfaces directly with telecom ASICs of that era. The 15 ns tpd easily handles 1.544/2.048 MHz TDM buses with margin. Note: for new designs, migrate to MAX V 5M570ZE64 or MAX II EPM240 CPLDs.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC240-15YY — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC240-15 | EPM9560RC240-15W | EPM9560RC240-15N | EPM9560RC240-15C | EPM9560RC240-12 | EPM9560ARC240-10 |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | RQFP-240 | RQFP-240 - same | RQFP-240 - same | RQFP-240 - same | RQFP-240 - same | RQFP-240 - same | RQFP-240 - same |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 | 560 |
| User I/O | 191 | 191 | 191 | 191 | 191 | 191 | 191 |
| Propagation Delay (tpd) | 15 ns | 15 ns | 15 ns | 15 ns | 15 ns | 12 ns (-20%) | 10 ns (-33%) |
| Maximum Frequency | 117.6 MHz | 117.6 MHz | 117.6 MHz | 117.6 MHz | 117.6 MHz | ~147 MHz (+25%) | ~176 MHz (+50%) |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| RoHS Compliance | Non-RoHS (YY suffix) | RoHS | RoHS | Pb-free | RoHS (industrial temp) | RoHS | RoHS |
Key Differentiators
- Non-RoHS lead finish variant (vs EPM9560RC240-15)
- 15 ns deterministic tpd across 560 macrocells (vs EPM9560ARC240-10)
- 191 user I/O in RQFP-240 package (vs EPM9560RC208-20)
Design Notes
The EPM9560RC240-15YY requires a clean 5.0 V VCC supply with +/-5% tolerance. Place a 0.1 uF X7R ceramic decoupling capacitor within 5 mm of every VCC/GND pair (24 VCC pins and 24 GND pins on the RQFP-240). Add a single 22 uF tantalum or 47 uF ceramic bulk capacitor near the package center. Estimated: at 50% toggle rate with 191 I/Os, ICC core current is approximately 300-400 mA, so budget 2-2.5 W worst-case dissipation and verify with the actual design toggle activity.
The RQFP-240 package has a 0.5 mm pitch and 32 mm body size; use 4-layer PCB with dedicated ground plane directly beneath the CPLD. All 24 GND pins must be soldered with low-impedance vias to the inner ground plane (at least 2 vias per GND pin). JTAG signals (TDI, TDO, TMS, TCK, TRST) should be routed as a 4-wire chain with 10 kohm pull-ups on TCK/TMS/TDI and a 10 kohm pull-down on TRST to prevent spurious configuration. Reserve a JTAG header even on production boards for in-field ISP.
Do not confuse the EPM9560RC240-15YY (non-RoHS) with the EPM9560RC240-15 (RoHS) - they are pin-compatible but may fail Pb-free reflow profiles if the YY suffix part is used. Also note that the MAX 9000A family is NRND; new designs should migrate to MAX V (5M570ZE64) or MAX II (EPM240) CPLDs, which require Quartus instead of MAX+PLUS II and have different footprints - PCB redesign will be required for the migration.
Compliance Information
YY suffix per Altera legacy ordering convention indicates non-RoHS lead finish (SnPb or matte-tin). Not AEC-Q100 qualified (CPLD, not an automotive-grade part by default). Reach, halogen-free, and conflict-mineral status not stated in available distributor data; marked unknown.
