EPM9560RC240-2 vs EPM9560RC240-3 Comparison
Detailed side-by-side comparison of EPM9560RC240-2 by Altera and EPM9560RC240-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC240-2 | EPM9560RC240-3 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Logic Elements | 560 macrocells | — |
| Usable Gates | 12,000 | 12000 |
| Pin-to-Pin Delay | 2 ns (speed grade -2) | — |
| Maximum Frequency | 100 MHz | — |
| Supply Voltage | 5 V | — |
| User I/O Count | 212 | — |
| Package | 240-pin RQFP (Metric QFP) | 240-pin RQFP (PowerQuad II) |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1), in-system programmable | — |
| Non-Volatile Configuration | Yes (EEPROM-based) | — |
| Operating Temperature | [DATA_NEEDED: commercial/industrial grade] | — |
| RoHS Status | Non-compliant (5V RQFP, pre-RoHS era) | [DATA_NEEDED: RoHS] |
| Lead-Free | No (legacy Sn/Pb process) | — |
| Logic Block Count | [DATA_NEEDED: LAB count] | — |
| Device Type | — | Complex Programmable Logic Device (CPLD) |
| Macrocells | — | 560 |
| Logic Array Blocks (LABs) | — | 20 |
| Pin-to-Pin Propagation Delay | — | 3 ns (speed grade -3) |
| Maximum Operating Frequency | — | [DATA_NEEDED: fMAX] |
| Supply Voltage (VCCINT) | — | 5 V |
| Supply Voltage (VCCIO) | — | 5 V |
| User I/O Pins | — | 192 |
| Configuration Memory | — | EEPROM (non-volatile) |
| Operating Temperature Range | — | 0C to +70C (commercial) |
| Lead Finish | — | [DATA_NEEDED: lead finish] |
| MSL Level | — | [DATA_NEEDED: MSL] |
| JTAG Support | — | [DATA_NEEDED: JTAG] |