EPM9560RC240-2 - MAX 9000 CPLD, 560 Macrocells, 240-RQFP | Altera
MPN: EPM9560RC240-2 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $224.8 | $224.80 |
| 10 | $202.32 | $2,023.20 |
| 100 | $202.32 | $20,232.00 |
| 500 | $195 | $97,500.00 |
| 1,000 | $180 | $180,000.00 |
Drop-in alternatives for EPM9560RC240-2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560RC240-15
✅ Drop-In✓ In Stock
$174.72 / Unit
View Datasheet →EPM9560RC240-10
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View Datasheet →EPM9560RC240-12
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$9.95 / Unit
View Datasheet →EPM9560RC240-15C
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View Datasheet →EPM9560RC240-15N
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$27.85 / Unit
View Datasheet →EPM9560RC240-15W
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View Datasheet →EPM9560RC240-2 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Logic Elements | 560 macrocells |
| Usable Gates | 12,000 |
| Pin-to-Pin Delay | 2 ns (speed grade -2) |
| Maximum Frequency | 100 MHz |
| Supply Voltage | 5 V |
| User I/O Count | 212 |
| Package | 240-pin RQFP (Metric QFP) |
| Mounting Type | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1), in-system programmable |
| Non-Volatile Configuration | Yes (EEPROM-based) |
| RoHS Status | Non-compliant (5V RQFP, pre-RoHS era) |
| Lead-Free | No (legacy Sn/Pb process) |
EPM9560RC240-2 240-pin rqfp (metric qfp) Pin Configuration Guide
Complete pinout information for EPM9560RC240-2 (240-pin rqfp (metric qfp) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC240-2.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC240-2 is suitable for 6 applications: Bus Interface Bridging, Address Decoding and Chip Select Logic, State Machine Controllers, Glue Logic Replacement, Peripheral Interface Controllers, Legacy System Sustainment.
Bus Interface Bridging
The EPM9560RC240-2's 560 macrocells and 212 user I/O pins make it ideal for bridging between legacy 5V peripheral buses and modern processors. Its 2 ns pin-to-pin delay enables single-cycle address decoding and chip-select generation with deterministic timing, which is critical for memory-mapped peripherals. The device's 5V tolerant MultiVolt I/O supports direct interfacing to TTL/CMOS peripherals without level shifters. Placed between a host CPU bus and multiple peripheral devices, the EPM9560RC240-2 can decode full 32-bit address spaces, generate wait-state insertion logic, and provide interrupt aggregation - all in a single non-volatile device that boots instantly on power-up.
Recommended
Address Decoding and Chip Select Logic
With 12,000 usable gates and 2 ns propagation delay, the EPM9560RC240-2 provides glitch-free address decoding for memory and peripheral subsystems requiring strict timing margins. The deterministic single-cycle delay outperforms FPGA implementations for synchronous decoding where setup/hold windows are tight. Used as a companion to a CPU/ASIC, the device can decode complex address maps with sub-3 ns latency, freeing the host processor from glue-logic overhead. The JTAG in-system programmability allows late-stage address-map revisions without PCB rework - critical during ASIC bring-up where peripheral base addresses often shift.
Recommended
State Machine Controllers
The EPM9560RC240-2's 560 macrocells support large multi-state controllers with 50+ states and complex conditional branching, while its 100 MHz fMAX enables high-speed sequential control loops. The EEPROM-based non-volatile configuration means state machines power up in a known valid state - critical for industrial controllers where undefined boot states could cause damage. Designers typically implement FSMs in VHDL/Verilog and synthesize via MAX+PLUS II, achieving timing closure in a single iteration thanks to the deterministic interconnect architecture. Each macrocell's dedicated flip-flop and product-term steering eliminate the routing bottlenecks seen in SRAM FPGAs.
Recommended
Glue Logic Replacement
The EPM9560RC240-2 excels at consolidating discrete 74-series TTL and CMOS glue logic into a single programmable device, reducing board area and BOM count. With 212 user I/O, it can replace dozens of discrete gates, latches, and muxes while adding design flexibility - the same PCB layout can support multiple product variants by reprogramming the CPLD. The 2 ns delay ensures timing-compatible replacement for fast TTL families like 74F and 74AS, while the 5V supply matches existing 5V system rails without level shifting. JTAG programming allows in-circuit updates during system integration without removing the chip.
Recommended
Peripheral Interface Controllers
The EPM9560RC240-2's high I/O count and fast propagation delay suit complex peripheral controllers such as SCSI, ISA, VME, or proprietary backplane interfaces. The 5V MultiVolt I/O directly drives legacy peripheral transceivers without external buffers. Designers can implement protocol state machines, DMA handshaking, and interrupt prioritization within the 12,000-gate capacity, consolidating what would otherwise require multiple PALs and discrete logic. The non-volatile EEPROM ensures the peripheral initializes correctly even after power glitches - important for storage and industrial-control applications where recovery from brown-outs must be deterministic.
Recommended
Legacy System Sustainment
The EPM9560RC240-2 is widely used to sustain legacy 5V industrial, aerospace, and military systems where board redesign is not economically feasible. With mature JTAG programming tools (MAX+PLUS II and Quartus) still available and extensive design IP libraries in circulation, the part remains the lowest-risk option for maintaining fielded equipment. The -2 speed grade (2 ns) is preferred for retrofits into systems originally designed around 74F-series TTL timing. Aftermarket distributors maintain inventory for sustainment programs with 10-20 year lifecycle requirements.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC240-2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC240-15 | EPM9560RC240-10 | EPM9560RC240-12 | EPM9560RC240-15C | EPM9560RC240-15N |
|---|---|---|---|---|---|---|
| Package | 240-pin RQFP | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Pin-to-Pin Delay | 2 ns | 15 ns | 10 ns | 12 ns | 15 ns | 15 ns |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Maximum Frequency | 100 MHz | ~60 MHz | ~80 MHz | ~70 MHz | ~60 MHz | ~60 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| User I/O | 212 | 212 | 212 | 212 | 212 | 212 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Approx. Unit Price (Qty 1) | $224.80 | $90-150 (aftermarket) | $150-200 (aftermarket) | $130-180 (aftermarket) | $90-150 (aftermarket) | $90-150 (aftermarket) |
Key Differentiators
- Fastest speed grade in MAX 9000 family (vs EPM9560RC240-15)
- Highest-density member of MAX 9000 (vs EPM9480RC240-15)
- Original RC revision, established tooling (vs EPM9560ARC240-10)
Design Notes
Estimated: at 100 MHz toggling 50% of the 212 I/O with 50 pF loads, dynamic current is approximately I = CVf = 50e-12 * 5 * 212 * 1e8 = ~5.3 A peak switching current. The EPM9560RC240-2 requires bulk decoupling of 100uF tantalum + 10uF ceramic near the 240-RQFP VCC pins, plus 0.1uF ceramic per VCC/GND pair distributed around the package. Inrush current during power-up with all I/O switching can exceed 3A steady-state, requiring a regulator capable of 4-5A peak.
The 240-pin RQFP package has 0.5 mm pitch leads requiring a 4-layer PCB with 0.2 mm-wide traces between pads. Use micro-vias (0.15 mm drill) to fan-out from the inner-row pads to inner signal layers. Place a continuous ground plane on layer 2 directly beneath the device to provide low-impedance return paths for the high-speed JTAG clock (TCK) up to 10 MHz. Decoupling capacitors should be placed within 5 mm of each VCC pin pair, with vias connecting to the ground plane at the capacitor pad to minimize loop inductance.
Route the four dedicated JTAG pins (TDI, TDO, TMS, TCK) as a matched-length bus to a 2x5 or 2x7 header per IEEE 1149.1. Keep TCK trace short (<50 mm) and well-grounded to avoid programming failures. The global clock pins should be routed with controlled impedance and isolated from switching I/O with ground guard traces to prevent jitter on internal flip-flops. Leave room around the device for a heat sink attachment - the 240-RQFP can dissipate 1.5-2 W under worst-case switching at 100 MHz.
Do not connect 5V signals to the JTAG pins when the device VCCIO is configured for 3.3V operation - use a level shifter or set VCCIO to 5V. Do not exceed the 5V supply tolerance; the MAX 9000 family is not 5V-tolerant on absolute-maximum scale (6V abs max). When migrating designs from -15 speed grade to the -2 grade, verify that signal integrity at the faster edge rates does not cause ground-bounce issues on shared buses - add series damping resistors if necessary.
Compliance Information
MAX 9000 family was launched in the 1990s before RoHS mandates; original RC240 packages use Sn/Pb lead finish. Some variants with 'N' suffix (e.g., EPM9560RC240-15N) are lead-free reissues for modern assembly compliance.
