EPM9560RC304-2 vs EPM9560RC304-15F Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC304-2 sa pamamagitan ng Intel at EPM9560RC304-15F sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM9560RC304-2 - MAX 9000 EPLD 12k Gates 304-pin RQFP | Intel / Altera
EPM9560RC304-2 ObsoleteAltera
EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F ObsoletePagsanggunian na paghahambing
| Parametro | EPM9560RC304-2 | EPM9560RC304-15F |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | CPLD (EPLD - Erasable PLD) | — |
| Usable Gates | Approximately 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 | 16 (40 macrocells each) |
| Macrocells | [DATA_NEEDED: macrocell count] | 560 |
| User I/O Pins | 304 | 212 |
| Packhaging | 304-pin RQFP (RC) | RQFP-304 (304-pin Plastic QFP) |
| Speed Grade | -2 | — |
| Core Supply Voltage | 5.0 V | 5.0 V |
| I/O Supply Voltage | 5.0 V | — |
| Programming Technology | EEPROM (in-system programmable) | 5.0 V in-system EEPROM via JTAG (IEEE 1149.1) |
| JTAG Support | IEEE Std. 1149.1 (boundary-scan + ISP) | — |
| Temperature na Operasyon | Commercial (0C to +70C) | -40C to +85C (industrial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status - not stated in source] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array MatriX (MAX) with PIA interconnect |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Device Family | — | MAX 9000 |
| Series | — | EPM9560 |
| Propagation Delay (tpd) | — | 16.6 ns (max) |
| Maximum Internal Frequency | — | 117.6 MHz |
| Dedicated Inputs | — | 4 |
| Boundary Scan Test (BST) | — | Yes, JTAG-compliant |
| Process Technology | — | High-performance CMOS, EEPROM-based |
| Level ng MSL | — | 3 (168 hours) |