EPM9560RI208-10N vs EPM9560ARI208-10N Comparison
Detailed side-by-side comparison of EPM9560RI208-10N by Altera and EPM9560ARI208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560ARI208-10N - MAX 9000 CPLD 12K Gates 560 Macrocells | Altera
EPM9560ARI208-10N ObsoleteSpecification Comparison
| Parameter | EPM9560RI208-10N | EPM9560ARI208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $61.75 | $22.10 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | β |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | β |
| Register Bits | 12,160 | β |
| User I/Os | 212 | β |
| Pin-to-Pin Delay | 10 ns (speed grade -10) | β |
| Maximum Frequency | 100 MHz to 125 MHz | β |
| Supply Voltage | 5 V | 5.0 V |
| Package | 208-pin RQFP (PQFP) | 208-pin RQFP (Plastic) |
| Operating Temperature | -40C to +85C (Industrial grade, "RI" suffix) | 0 C to 70 C (Commercial) |
| Programming Method | In-system via IEEE 1149.1 (JTAG) | β |
| MSL Level | 3 (168 Hours) | β |
| RoHS Status | ROHS3 Compliant (per fpgalink) | β |
| Configuration Memory | On-chip EEPROM (non-volatile) | β |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 560 |
| Logic Array Blocks (LABs) | β | 35 |
| Maximum User I/O Pins | β | 212 |
| Flip-Flops | β | 484 |
| Propagation Delay (tPD1) | β | 10 ns |
| Clock-to-Output (tCO) | β | 4.5 ns |
| Setup Time (tSU) | β | 3.0 ns |
| Maximum Counter Frequency (fCNT) | β | 144.9 MHz |
| Logic Family | β | CMOS EEPROM |
| Programming Interface | β | JTAG (IEEE 1149.1) - In-System Programmable |
| Mounting Type | β | Surface Mount |