EPM9560WC208-15 vs EPM9560WI208-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560WC208-15 sa pamamagitan ng Altera at EPM9560WI208-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560WC208-15 | EPM9560WI208-20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 9000 | — |
| Device Type | EE PLD (Electrically Erasable Programmable Logic Device) | EE PLD / Complex Programmable Logic Device (CPLD) |
| Technology | CMOS | — |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 35 | 16 |
| Flip-Flops | 772 | — |
| User I/O Pins (max) | 149 | — |
| Maksimum na Taktiko ng Oras | 117.6 MHz | — |
| Propagation Delay (tPD) | 16.6 ns | — |
| Speed Grade | -15 | -20 |
| Supply Voltage - I/O | 3.3 V or 5.0 V (configurable) | — |
| Packhaging | 208-pin CQFP (Ceramic Quad Flat Pack) | — |
| Terminal Pitch | 0.50 mm | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | — |
| Tindminan RoHS | RoHS3 Compliant (per third-party listings) | — |
| Device Family | — | MAX 9000 |
| Macrocells / Logic Cells | — | 560 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Propagation Delay (tPD) | — | 23.6 ns |
| Process Technology | — | 0.35 micron CMOS EEPROM |
| Programmability | — | In-system via JTAG (IEEE 1149.1) |
| Package Type | — | CQFP-208 (Ceramic Quad Flat Pack) |
| Terminal Form | — | Gull Wing |
| Number of Terminals | — | 208 |
| Package Code | — | QFP |
| Package Shape | — | Square |
| Operating Temperature Grade | — | Industrial |
| Design Tools | — | MAX+PLUS II, Quartus |
| Compliance | — | [DATA_NEEDED: RoHS status] |