EPM9560WC208 vs EPM9560WC208-20 Comparison
Detailed side-by-side comparison of EPM9560WC208 by Altera and EPM9560WC208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560WC208-20 - 560-Macrocell CPLD, 23.6ns, PQFP-208 | Intel/Altera
EPM9560WC208-20 ObsoleteSpecification Comparison
| Parameter | EPM9560WC208 | EPM9560WC208-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE Programmable Logic Device (CPLD) | CPLD (EPLD) |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 35 |
| Flip-Flops | 772 | — |
| Maximum User I/O | 149 | — |
| Maximum Clock Frequency | 117.6 MHz | — |
| Propagation Delay (tpd, -15 grade) | 16.6 ns | — |
| Supply Voltage | 3.3 V or 5 V | — |
| Process Technology | CMOS, electrically erasable | CMOS, EEPROM-based |
| Package | 208-pin CQFP (Ceramic Quad Flat Pack) | PQFP-208 (RQFP/WQFP) |
| Terminal Pitch | 0.50 mm | — |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Configuration Memory | Non-volatile EE (instant-on) | — |
| Hot Socketing Support | Yes | — |
| MSL Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED] |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc] |
| User I/O Pins | — | 149 |
| Maximum Propagation Delay (tPD) | — | 23.6 ns |
| Supply Voltage (VCCINT) | — | 5 V (typical, see datasheet) |
| I/O Voltage (VCCIO) | — | 3.3 V or 5 V (multi-voltage I/O) |
| In-System Programmability | — | Yes, JTAG BST (IEEE 1149.1) |
| Pin/Package Suffix | — | W = power PQFP; -20 = 23.6 ns speed grade |
| Operating Temperature | — | Commercial (0C to +70C) [DATA_NEEDED: exact temp grade] |
| Lead-Free | — | [DATA_NEEDED] |
| Halogen Free | — | [DATA_NEEDED] |