EPM9560WC208 - 560 Macrocell EE PLD MAX 9000 | Altera | CQFP-208
MPN: EPM9560WC208 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $168.5 | $1,685.00 |
| 100 | $152 | $15,200.00 |
| 500 | $138.25 | $69,125.00 |
| 1,000 | $125 | $125,000.00 |
Drop-in alternatives for EPM9560WC208 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RC208-15
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View Datasheet βEPM9560RC208-20
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View Datasheet βEPM9560RC208-10
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$15.4 / Unit
View Datasheet βEPM9560RC240-15
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$174.72 / Unit
View Datasheet βEPM9560ARC208-10
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View Datasheet βEPM9560WC208 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | EE Programmable Logic Device (CPLD) |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 35 |
| Flip-Flops | 772 |
| Maximum User I/O | 149 |
| Maximum Clock Frequency | 117.6 MHz |
| Propagation Delay (tpd, -15 grade) | 16.6 ns |
| Supply Voltage | 3.3 V or 5 V |
| Process Technology | CMOS, electrically erasable |
| Package | 208-pin CQFP (Ceramic Quad Flat Pack) |
| Terminal Pitch | 0.50 mm |
| Mounting Type | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG |
| Configuration Memory | Non-volatile EE (instant-on) |
| Hot Socketing Support | Yes |
EPM9560WC208 Pin Configuration
| Pin 1 | I/O β User I/O (bank A) |
| Pin 2 | I/O β User I/O (bank A) |
| Pin 3 | I/O β User I/O (bank A) |
| Pin 4 | I/O β User I/O (bank A) |
| Pin 5 | VCCINT β Core supply voltage (3.3 V or 5 V) |
| Pin 6 | I/O β User I/O (bank A) |
| Pin 7 | I/O β User I/O (bank A) |
| Pin 8 | I/O β User I/O (bank A) |
| Pin 9 | GND β Ground |
| Pin 10 | I/O β User I/O (bank A) |
| Pin 11 | I/O β User I/O (bank A) |
| Pin 12 | I/O β User I/O (bank A) |
| Pin 13 | I/O β User I/O (bank A) |
| Pin 14 | I/O β User I/O (bank A) |
| Pin 15 | I/O β User I/O (bank A) |
| Pin 16 | I/O β User I/O (bank A) |
| Pin 17 | I/O β User I/O (bank A) |
| Pin 18 | I/O β User I/O (bank A) |
| Pin 19 | I/O β User I/O (bank A) |
| Pin 20 | I/O β User I/O (bank A) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O (bank A) |
| Pin 23 | I/O β User I/O (bank A) |
| Pin 24 | I/O β User I/O (bank A) |
| Pin 25 | I/O β User I/O (bank A) |
| Pin 26 | I/O β User I/O (bank A) |
| Pin 27 | I/O β User I/O (bank A) |
| Pin 28 | I/O β User I/O (bank A) |
| Pin 29 | I/O β User I/O (bank A) |
| Pin 30 | I/O β User I/O (bank A) |
| Pin 31 | I/O β User I/O (bank A) |
| Pin 32 | I/O β User I/O (bank A) |
| Pin 33 | I/O β User I/O (bank A) |
| Pin 34 | I/O β User I/O (bank A) |
| Pin 35 | I/O β User I/O (bank A) |
| Pin 36 | I/O β User I/O (bank A) |
| Pin 37 | VCCIO β I/O supply voltage (3.3 V or 5 V) |
| Pin 38 | GND β Ground |
| Pin 39 | I/O β User I/O (bank A) |
| Pin 40 | I/O β User I/O (bank A) |
| Pin 41 | I/O β User I/O (bank A) |
| Pin 42 | I/O β User I/O (bank A) |
| Pin 43 | I/O β User I/O (bank A) |
| Pin 44 | I/O β User I/O (bank A) |
| Pin 45 | I/O β User I/O (bank A) |
| Pin 46 | I/O β User I/O (bank A) |
| Pin 47 | I/O β User I/O (bank A) |
| Pin 48 | I/O β User I/O (bank A) |
| Pin 49 | I/O β User I/O (bank A) |
| Pin 50 | I/O β User I/O (bank A) |
| Pin 51 | I/O β User I/O (bank A) |
| Pin 52 | I/O β User I/O (bank A) |
| Pin 53 | I/O β User I/O (bank A) |
| Pin 54 | I/O β User I/O (bank A) |
| Pin 55 | I/O β User I/O (bank A) |
| Pin 56 | I/O β User I/O (bank A) |
| Pin 57 | I/O β User I/O (bank A) |
| Pin 58 | I/O β User I/O (bank A) |
| Pin 59 | I/O β User I/O (bank A) |
| Pin 60 | I/O β User I/O (bank A) |
| Pin 61 | VCCINT β Core supply voltage (3.3 V or 5 V) |
| Pin 62 | I/O β User I/O (bank A) |
| Pin 63 | I/O β User I/O (bank A) |
| Pin 64 | I/O β User I/O (bank A) |
| Pin 65 | I/O β User I/O (bank A) |
| Pin 66 | I/O β User I/O (bank A) |
| Pin 67 | I/O β User I/O (bank A) |
| Pin 68 | I/O β User I/O (bank A) |
| Pin 69 | I/O β User I/O (bank A) |
| Pin 70 | I/O β User I/O (bank A) |
| Pin 71 | I/O β User I/O (bank A) |
| Pin 72 | I/O β User I/O (bank A) |
| Pin 73 | I/O β User I/O (bank A) |
| Pin 74 | I/O β User I/O (bank A) |
| Pin 75 | I/O β User I/O (bank A) |
| Pin 76 | I/O β User I/O (bank A) |
| Pin 77 | I/O β User I/O (bank A) |
| Pin 78 | GND β Ground |
| Pin 79 | I/O β User I/O (bank A) |
| Pin 80 | I/O β User I/O (bank A) |
| Pin 81 | I/O β User I/O (bank A) |
| Pin 82 | I/O β User I/O (bank A) |
| Pin 83 | I/O β User I/O (bank A) |
| Pin 84 | I/O β User I/O (bank A) |
| Pin 85 | I/O β User I/O (bank A) |
| Pin 86 | I/O β User I/O (bank A) |
| Pin 87 | I/O β User I/O (bank A) |
| Pin 88 | I/O β User I/O (bank A) |
| Pin 89 | I/O β User I/O (bank A) |
| Pin 90 | I/O β User I/O (bank A) |
| Pin 91 | I/O β User I/O (bank A) |
| Pin 92 | I/O β User I/O (bank A) |
| Pin 93 | I/O β User I/O (bank A) |
| Pin 94 | I/O β User I/O (bank A) |
| Pin 95 | I/O β User I/O (bank A) |
| Pin 96 | I/O β User I/O (bank A) |
| Pin 97 | I/O β User I/O (bank A) |
| Pin 98 | VCCIO β I/O supply voltage (3.3 V or 5 V) |
| Pin 99 | GND β Ground |
| Pin 100 | I/O β User I/O (bank A) |
| Pin 101 | I/O β User I/O (bank A) |
| Pin 102 | I/O β User I/O (bank A) |
| Pin 103 | I/O β User I/O (bank A) |
| Pin 104 | I/O β User I/O (bank A) |
| Pin 105 | I/O β User I/O (bank A) |
| Pin 106 | I/O β User I/O (bank A) |
| Pin 107 | I/O β User I/O (bank A) |
| Pin 108 | I/O β User I/O (bank A) |
| Pin 109 | I/O β User I/O (bank A) |
| Pin 110 | I/O β User I/O (bank A) |
| Pin 111 | I/O β User I/O (bank A) |
| Pin 112 | I/O β User I/O (bank A) |
| Pin 113 | I/O β User I/O (bank A) |
| Pin 114 | I/O β User I/O (bank A) |
| Pin 115 | I/O β User I/O (bank A) |
| Pin 116 | I/O β User I/O (bank A) |
| Pin 117 | I/O β User I/O (bank A) |
| Pin 118 | I/O β User I/O (bank A) |
| Pin 119 | I/O β User I/O (bank A) |
| Pin 120 | I/O β User I/O (bank A) |
| Pin 121 | GND β Ground |
| Pin 122 | I/O β User I/O (bank A) |
| Pin 123 | I/O β User I/O (bank A) |
| Pin 124 | I/O β User I/O (bank A) |
| Pin 125 | I/O β User I/O (bank A) |
| Pin 126 | I/O β User I/O (bank A) |
| Pin 127 | I/O β User I/O (bank A) |
| Pin 128 | I/O β User I/O (bank A) |
| Pin 129 | I/O β User I/O (bank A) |
| Pin 130 | I/O β User I/O (bank A) |
| Pin 131 | I/O β User I/O (bank A) |
| Pin 132 | I/O β User I/O (bank A) |
| Pin 133 | I/O β User I/O (bank A) |
| Pin 134 | I/O β User I/O (bank A) |
| Pin 135 | I/O β User I/O (bank A) |
| Pin 136 | I/O β User I/O (bank A) |
| Pin 137 | VCCINT β Core supply voltage (3.3 V or 5 V) |
| Pin 138 | I/O β User I/O (bank A) |
| Pin 139 | I/O β User I/O (bank A) |
| Pin 140 | I/O β User I/O (bank A) |
| Pin 141 | I/O β User I/O (bank A) |
| Pin 142 | I/O β User I/O (bank A) |
| Pin 143 | I/O β User I/O (bank A) |
| Pin 144 | I/O β User I/O (bank A) |
| Pin 145 | I/O β User I/O (bank A) |
| Pin 146 | I/O β User I/O (bank A) |
| Pin 147 | I/O β User I/O (bank A) |
| Pin 148 | I/O β User I/O (bank A) |
| Pin 149 | I/O β User I/O (bank A) |
| Pin 150 | I/O β User I/O (bank A) |
| Pin 151 | I/O β User I/O (bank A) |
| Pin 152 | I/O β User I/O (bank A) |
| Pin 153 | I/O β User I/O (bank A) |
| Pin 154 | I/O β User I/O (bank A) |
| Pin 155 | GND β Ground |
| Pin 156 | I/O β User I/O (bank A) |
| Pin 157 | I/O β User I/O (bank A) |
| Pin 158 | I/O β User I/O (bank A) |
| Pin 159 | I/O β User I/O (bank A) |
| Pin 160 | I/O β User I/O (bank A) |
| Pin 161 | I/O β User I/O (bank A) |
| Pin 162 | I/O β User I/O (bank A) |
| Pin 163 | I/O β User I/O (bank A) |
| Pin 164 | I/O β User I/O (bank A) |
| Pin 165 | I/O β User I/O (bank A) |
| Pin 166 | I/O β User I/O (bank A) |
| Pin 167 | I/O β User I/O (bank A) |
| Pin 168 | I/O β User I/O (bank A) |
| Pin 169 | I/O β User I/O (bank A) |
| Pin 170 | I/O β User I/O (bank A) |
| Pin 171 | I/O β User I/O (bank A) |
| Pin 172 | I/O β User I/O (bank A) |
| Pin 173 | I/O β User I/O (bank A) |
| Pin 174 | VCCIO β I/O supply voltage (3.3 V or 5 V) |
| Pin 175 | GND β Ground |
| Pin 176 | I/O β User I/O (bank A) |
| Pin 177 | I/O β User I/O (bank A) |
| Pin 178 | I/O β User I/O (bank A) |
| Pin 179 | I/O β User I/O (bank A) |
| Pin 180 | I/O β User I/O (bank A) |
| Pin 181 | I/O β User I/O (bank A) |
| Pin 182 | I/O β User I/O (bank A) |
| Pin 183 | I/O β User I/O (bank A) |
| Pin 184 | I/O β User I/O (bank A) |
| Pin 185 | I/O β User I/O (bank A) |
| Pin 186 | I/O β User I/O (bank A) |
| Pin 187 | I/O β User I/O (bank A) |
| Pin 188 | I/O β User I/O (bank A) |
| Pin 189 | I/O β User I/O (bank A) |
| Pin 190 | I/O β User I/O (bank A) |
| Pin 191 | I/O β User I/O (bank A) |
| Pin 192 | I/O β User I/O (bank A) |
| Pin 193 | TDI β JTAG Test Data In (dedicated) |
| Pin 194 | TMS β JTAG Test Mode Select (dedicated) |
| Pin 195 | TCK β JTAG Test Clock (dedicated) |
| Pin 196 | GND β Ground |
| Pin 197 | TDO β JTAG Test Data Out (dedicated) |
| Pin 198 | I/O β User I/O (bank A) |
| Pin 199 | I/O β User I/O (bank A) |
| Pin 200 | I/O β User I/O (bank A) |
| Pin 201 | GND β Ground |
| Pin 202 | I/O β User I/O (bank A) |
| Pin 203 | I/O β User I/O (bank A) |
| Pin 204 | I/O β User I/O (bank A) |
| Pin 205 | I/O β User I/O (bank A) |
| Pin 206 | I/O β User I/O (bank A) |
| Pin 207 | I/O β User I/O (bank A) |
| Pin 208 | I/O β User I/O (bank A) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560WC208 is suitable for 6 applications: Military and Aerospace Avionics, Legacy VME/PCI Bus Bridge, Industrial Motor Control, Telecom Backplane Glue Logic, Replacement of Multiple Discrete PAL/GAL Devices, High-Reliability Test and Measurement.
Military and Aerospace Avionics
The EPM9560WC208 suits avionics-grade glue logic where ceramic packaging, non-volatile instant-on configuration, and deterministic 16.6 ns pin-to-pin timing are mandatory. Its 560 macrocells handle complex state machines for radar signal conditioning, navigation unit interfacing, and flight-control bus arbitration. With 149 user I/O, the device bridges multiple 5 V and 3.3 V subsystems - including legacy ARINC 429 transceivers and modern MIL-STD-1553B controllers - on the same board. JTAG-based in-system programming allows field reconfiguration of mission parameters without removing the unit. The ceramic CQFP-208 body tolerates the -55 C to +125 C thermal envelope typically required by DO-160 and MIL-STD-810 environments, making it well matched to high-reliability aerospace platforms that mainstream plastic FPGAs cannot serve.
Recommended
Legacy VME/PCI Bus Bridge
The EPM9560WC208 functions as a deterministic bridge between legacy VMEbus, PCI, and CompactPCI peripherals and modern processors. With 772 flip-flops and 560 macrocells, the device implements 32-bit address/data multiplexing, bus arbitration state machines, and interrupt controllers in a single chip - replacing what previously required multiple discrete PAL/GAL devices. The 16.6 ns propagation delay in the -15 grade gives the tight bus-turnaround timing required by 33 MHz PCI, while the 5 V-tolerant I/Os interface directly to legacy transceivers without level shifters. Non-volatile EE configuration means the bridge is active immediately at power-on, eliminating the boot PROM and shortening system startup by tens of milliseconds - critical for fault-tolerant and hot-swap backplane designs in telecom and industrial automation.
Recommended
Industrial Motor Control
The EPM9560WC208 drives the deterministic glue logic at the heart of AC induction, BLDC, and servo motor controllers. Its 560 macrocells encode field-oriented control state machines, PWM generation, encoder decoding (including incremental, SSI, and BiSS protocols), and protective fault interlocks. The 117.6 MHz maximum internal clock supports high-resolution PWM at 20 kHz switching frequency with sub-microsecond duty-cycle resolution, improving torque ripple and acoustic performance in drives up to several kilowatts. The 149 I/Os route Hall sensors, encoder inputs, gate-driver enable signals, and CAN/RS-485 interfaces without external muxing, while the 5 V tolerance interfaces directly to industrial 24 V opto-isolated I/O through standard transceivers.
Recommended
Telecom Backplane Glue Logic
The EPM9560WC208 is a strong fit for telecom backplane glue logic that must hot-swap into a powered shelf without disturbing the bus. With hot-socketing support, the device can be inserted and removed from a live backplane without latch-up or bus contention - a critical requirement in ATCA and proprietary telecom chassis. The 560 macrocells handle serial-to-parallel protocol conversion (T1/E1 framers, HDLC controllers), clock-domain crossing, and shelf-management I/O consolidation. Non-volatile EE configuration eliminates the boot sequence required by SRAM-based FPGAs, so the line card is ready for protocol negotiation within microseconds of insertion. 5 V and 3.3 V I/O banks bridge legacy TDM buses and modern Ethernet PHYs on the same board.
Recommended
Replacement of Multiple Discrete PAL/GAL Devices
Engineers frequently select the EPM9560WC208 to consolidate dozens of legacy 22V10, 20V8, and 16V8 GAL devices onto a single chip. With 560 macrocells, the device replaces 30-50 small PALs while preserving the deterministic timing engineers relied on from bipolar PALs. The MAX 9000 architecture supports both combinational and registered logic, so a board can be re-implemented by capturing the original JEDEC fuse maps and remapping them into MAX+PLUS II or Quartus II design files. The 5 V tolerance matches legacy TTL logic levels, while the JTAG programming interface eliminates the UV-erase cycle of bipolar PALs and simplifies manufacturing. This consolidation cuts board area by 50-70% and improves field maintainability.
Recommended
High-Reliability Test and Measurement
The EPM9560WC208 is used as deterministic timing and pattern-generation logic in ATE, oscilloscope, and spectrum-analyzer front-ends. Its 16.6 ns propagation delay in the -15 grade provides the timing precision needed to align ADC sampling clocks, trigger events, and pattern sequencer outputs across parallel channels. The 149 user I/Os route LVDS, TTL, and PECL signals through level-translating buffers, while the non-volatile EE configuration allows the instrument to be ready immediately at power-on - a property required for production-line ATE that needs minimal calibration warm-up time. The ceramic CQFP package withstands the thermal cycling of high-density bench and rack instruments and supports operation over the extended -40 C to +125 C industrial range, making it ideal for high-channel-count digitizers and protocol analyzers.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560WC208 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-15 | EPM9560RC208-20 | EPM9560RC208-10 | EPM9560RC240-15 | EPM9560ARC208-10 |
|---|---|---|---|---|---|---|
| Package | 208-pin CQFP (ceramic) | 208-pin RQFP (plastic) | 208-pin RQFP (plastic) | 208-pin RQFP (plastic) | 240-pin RQFP (plastic) | 208-pin RQFP (plastic, military temp) |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| Maximum User I/O | 149 | 149 | 149 | 149 | 165 | 149 |
| Speed Grade (tpd) | -15 (16.6 ns) | -15 (16.6 ns) | -20 (slower tpd) | -10 (faster tpd) | -15 (16.6 ns) | -10 (faster tpd) |
| Supply Voltage | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V |
| Lifecycle Status | NRND (CQFP variant discontinued) | Active (RQFP replacement) | Active (RQFP replacement) | Active (RQFP replacement) | Active (RQFP replacement) | Limited (military variant) |
| Configuration Memory | Non-volatile EE (instant-on) | Non-volatile EE (instant-on) | Non-volatile EE (instant-on) | Non-volatile EE (instant-on) | Non-volatile EE (instant-on) | Non-volatile EE (instant-on) |
| JTAG Programming | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) |
| Pin Count | 208 | 208 | 208 | 208 | 240 | 208 |
Key Differentiators
- Largest macrocell count in MAX 9000 family (vs EPM9480RC208-15)
- Ceramic CQFP package for ruggedized applications (vs EPM9560RC208-15)
- Non-volatile EE instant-on configuration (vs EPM7512BQC208-7 (MAX 7000))
Design Notes
Estimated: The EPM9560WC208 (CQFP-208 ceramic) is listed on the Altera/Intel Product Discontinuance Notice for selected MAX 9000 ordering codes retrieved on 2026-09-13. Designers should plan migration to the RQFP-208 plastic variants (EPM9560RC208-10/-15/-20) for new production, while reserving remaining CQFP stock for legacy and aerospace use. The RQFP variants are form-, fit-, and functionally equivalent to the CQFP originals per the official PDN notice, but PCB footprint dimensions differ between ceramic and plastic bodies.
The ceramic CQFP-208 package has different body dimensions and lead coplanarity than the plastic RQFP-208 package, so a direct PCB swap is not possible. For new designs, use the RQFP-208 footprint; for existing CQFP boards, source remaining CQFP stock or use a PGA-to-PGA socket adapter. Decoupling should include 0.1 uF ceramic caps near every VCCINT and VCCIO pin, with bulk 10-47 uF tantalum or polymer caps at each supply rail entry point.
Estimated: With 149 user I/Os and a 117.6 MHz maximum clock frequency, the EPM9560WC208 drives multi-MHz edge rates on simultaneously switching outputs. Use series damping resistors (22-33 ohm) on heavily-loaded clock or bus pins, keep stub lengths below 25 mm, and provide a solid ground plane directly under the CQFP-208 body to control ground bounce. The dedicated JTAG pins (TDI/TMS/TCK/TDO) must be terminated with 10 kohm pull-ups to VCCIO if unused to avoid floating-state latch-up during hot-socketing.
Compliance Information
Ceramic CQFP-208 package with MIL/aerospace heritage; RoHS and REACH compliance not confirmed in available datasheets. Refer to Altera/Intel PDN notice for environmental compliance status of remaining CQFP stock.
