MCIMX31CVMN4CR2 vs MCIMX31LCVMN4C Comparison
Detailed side-by-side comparison of MCIMX31CVMN4CR2 by NXP Semiconductors and MCIMX31LCVMN4C by NXP Semiconductors. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
NXP Semiconductors
MCIMX31CVMN4CR2 - i.MX31 ARM1136 400MHz MPU, 473-LFBGA | NXP
MCIMX31CVMN4CR2 NrndNXP Semiconductors
MCIMX31LCVMN4C - i.MX31L ARM1136 400MHz MPU, MAPBGA-457 | NXP
MCIMX31LCVMN4C ⚠ Last Time BuySpecification Comparison
| Parameter | MCIMX31CVMN4CR2 | MCIMX31LCVMN4C |
|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors |
| Category | Microcontrollers | Microcontrollers |
| Lifecycle Status | NRND | Last Time Buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.10 | $10.50 |
| Core Architecture | ARM1136JF-S | ARM1136JF-S |
| Core Count | 1 | 1 |
| Data Bus Width | 32-bit | 16-bit |
| Maximum Core Frequency | 400 MHz | — |
| Operating Supply Voltage | 1.8 V to 2.0 V core, 1.8 V to 3.3 V I/O | — |
| Package / Case | 473-LFBGA (MAPBGA-473) | — |
| Package Dimensions | 19 mm x 19 mm | 14 x 14 mm |
| Mounting Type | Surface Mount | Surface Mount |
| RAM Size (on-chip SRAM) | 16K x 8 | — |
| Packaging | Tape & Reel (TR) | — |
| Oscillator Type | External | — |
| On-chip Multimedia | MPEG-4/H.263 encoder/decoder, Image Processing Unit (IPU) | — |
| Peripheral Interfaces | USB, Ethernet MAC, UART, I2C, SPI, MMC/SD | — |
| Operating Temperature Range | -40 C to +85 C (automotive/industrial grade) | -40C to +85C |
| Family | i.MX31 multimedia applications processors | i.MX31L |
| RoHS Status | Compliant | Compliant |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free and halogen-free status] | — |
| Maximum Clock Frequency | — | 400 MHz |
| Package Type | — | MAPBGA-457 |
| Ball Pitch | — | 0.5 mm |
| Pin Count | — | 457 |
| Variant Suffix | — | N4C (industrial/auto temp grade) |
| Process Node | — | [DATA_NEEDED: process node] |
| L1 Cache | — | [DATA_NEEDED: L1 instruction/data cache] |
| L2 Cache | — | [DATA_NEEDED: L2 cache] |
| Integrated LCD Controller | — | Yes |
| USB Interface | — | USB 2.0 with on-chip PHY |
| Image Processing Unit (IPU) | — | Yes |
| AEC-Q100 Grade | — | Grade 3 |