RTAX2000S-CGS624V vs RTAX2000SL-CGS624V Comparison
Detailed side-by-side comparison of RTAX2000S-CGS624V by Microchip Technology and RTAX2000SL-CGS624V by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Microchip Technology
RTAX2000S-CGS624V - 2M-Gate Rad-Tolerant FPGA CG624 | Microchip
RTAX2000S-CGS624V ✓ ActiveMicrochip Technology
RTAX2000SL-CGS624V - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000SL-CGS624V ✓ ActiveSpecification Comparison
| Parameter | RTAX2000S-CGS624V | RTAX2000SL-CGS624V |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $6,500.00 |
| Equivalent System Gates | 2000000 | 2000000 |
| Configurable Logic Blocks (CLBs) | 21504 | — |
| Logic Cells | 32256 | — |
| Technology | Digital CMOS, anti-fuse OTP | CMOS antifuse (nonvolatile) |
| Core Supply Voltage (Nominal) | 1.5 V | — |
| Core Supply Voltage Range | 1.425 V to 1.575 V | — |
| Operating Temperature | -55C to +125C | [DATA_NEEDED: operating temperature range] |
| Package | CG624 ceramic column grid array | CG624 ceramic package |
| Mounting Type | Surface Mount | — |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | RTAX-S/SL Radiation-Tolerant FPGA |
| Configuration Type | One-Time Programmable (anti-fuse), live at power-up | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | 540 kbits with optional EDAC protection |
| Clocking | Segmentable clocks | — |
| Routing Features | Chip-wide highway routing, carry logic | — |
| Application Domain | Space-flight systems | Space-flight systems |
| Max Family Density | 4000000 equivalent system gates (family max) | — |
| Logic Cells (CLBs) | — | 21504 |
| User I/Os (maximum) | — | 684 |
| Total Ionizing Dose (TID) | — | 300 krad (Si) functional / 200 krad (Si) parametric |
| Single-Event Upset Rate | — | Less than 1E-10 errors per bit-day |
| Configuration | — | One-time programmable antifuse, live at power-up |
| Embedded SRAM Features | — | Built-in FIFO control logic |
| Clock Architecture | — | Segmentable clock structures |
| Routing | — | Chip-wide highway routing, carry logic |
| Core Supply Voltage | — | [DATA_NEEDED: core supply voltage] |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O supply voltage] |
| Speed Grade | — | [DATA_NEEDED: speed grade] |
| System Frequency (typical) | — | [DATA_NEEDED: system frequency] |