RTAX2000S-CGS624V vs RTAX2000SL-CGS624V Comparaison
Comparaison détaillée côte à côte de RTAX2000S-CGS624V par Microchip Technology et RTAX2000SL-CGS624V par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
RTAX2000S-CGS624V - 2M-Gate Rad-Tolerant FPGA CG624 | Microchip
RTAX2000S-CGS624V ✓ ActifMicrochip Technology
RTAX2000SL-CGS624V - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000SL-CGS624V ✓ ActifComparaison des spécifications
| Paramètre | RTAX2000S-CGS624V | RTAX2000SL-CGS624V |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $6 500,00 |
| Equivalent System Gates | 2000000 | 2000000 |
| Configurable Logic Blocks (CLBs) | 21504 | — |
| Logic Cells | 32256 | — |
| Technology | Digital CMOS, anti-fuse OTP | CMOS antifuse (nonvolatile) |
| Core Supply Voltage (Nominal) | 1.5 V | — |
| Core Supply Voltage Range | 1.425 V to 1.575 V | — |
| Température de fonctionnement | -55C to +125C | [DATA_NEEDED: operating temperature range] |
| Boîtier | CG624 ceramic column grid array | CG624 ceramic package |
| Type de montage | Surface Mount | — |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | RTAX-S/SL Radiation-Tolerant FPGA |
| Configuration Type | One-Time Programmable (anti-fuse), live at power-up | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | 540 kbits with optional EDAC protection |
| Clocking | Segmentable clocks | — |
| Routing Features | Chip-wide highway routing, carry logic | — |
| Application Domain | Space-flight systems | Space-flight systems |
| Max Family Density | 4000000 equivalent system gates (family max) | — |
| Logic Cells (CLBs) | — | 21504 |
| User I/Os (maximum) | — | 684 |
| Total Ionizing Dose (TID) | — | 300 krad (Si) functional / 200 krad (Si) parametric |
| Single-Event Upset Rate | — | Less than 1E-10 errors per bit-day |
| Configuration | — | One-time programmable antifuse, live at power-up |
| Embedded SRAM Features | — | Built-in FIFO control logic |
| Clock Architecture | — | Segmentable clock structures |
| Routing | — | Chip-wide highway routing, carry logic |
| Core Supply Voltage | — | [DATA_NEEDED: core supply voltage] |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O supply voltage] |
| Speed Grade | — | [DATA_NEEDED: speed grade] |
| System Frequency (typical) | — | [DATA_NEEDED: system frequency] |