SN65LVDS105PWR vs TD1205 Comparison

Detailed side-by-side comparison of SN65LVDS105PWR by Texas Instruments and TD1205 by TD next. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Texas Instruments
SN65LVDS105PWR SN65LVDS105PWR - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI

SN65LVDS105PWR - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI

SN65LVDS105PWR ✓ Active

Specification Comparison

Parameter SN65LVDS105PWR TD1205
Brand Texas Instruments TD next
Category Clock & Timing RF Modules
Lifecycle Status Active Active
Stock Status In Stock In Stock
Unit Price (USD) $1.28 $10.50
Function 1 LVTTL input to 4 LVDS output repeater / fanout buffer —
Data Rate 400 Mbps —
Max Clock Frequency 400 MHz —
Supply Voltage 3 V to 3.6 V (typical 3.3 V) [DATA_NEEDED: VBAT operating range]
Input Type LVTTL (single-ended) —
Output Type LVDS (differential), 4 pairs —
Output Voltage (typical) 350 mV into 100 ohm load —
Standard Compliance ANSI EIA/TIA-644 LVDS —
Channels 1 x 1:4 —
Package 16-TSSOP (PW) —
Mounting Type Surface Mount Surface Mount (reflow)
Technology LVDS differential signaling —
Category Signal Buffers, Repeaters, Splitters - Clock Buffer —
Operating Temperature [DATA_NEEDED: operating temperature range] -40C to +85C
Quiescent Current [DATA_NEEDED: quiescent current] —
Input Rise/Fall Time Note TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance —
Product Type — Sigfox-certified RF transceiver module
Manufacturer — TD next (Telecom Design)
RF Protocol — Sigfox (Ultra-Narrow-Band LPWAN)
Operating Frequency (RC1) — 868 MHz (ETSI Europe)
Operating Frequency (RC2) — 902-928 MHz (US, Australia, Japan)
Tx Power (RC1) — +14 dBm typical
Tx Power (RC2) — +22 dBm maximum
Receiver Sensitivity — [DATA_NEEDED: receiver sensitivity]
Integrated Microcontroller — ARM Cortex-M0+ (STM32 family)
Clock Reference — Integrated TCXO
Host Interface — UART, SPI, I2C, GPIO
Modulation — Ultra-Narrow-Band (UNB), DBPSK uplink
Maximum Payload Size — 12 bytes per uplink message
Form Factor — Surface-mount LGA castellation module
RoHS Status — Compliant

Datasheets & Resources

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