SN65LVDS105PWR vs TD1205 Vergleich

Detaillierter Direktvergleich von SN65LVDS105PWR von Texas Instruments und TD1205 von TD next. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Texas Instruments
SN65LVDS105PWR SN65LVDS105PWR - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI

SN65LVDS105PWR - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI

SN65LVDS105PWR ✓ Aktiv

Spezifikationsvergleich

Parameter SN65LVDS105PWR TD1205
Marke Texas Instruments TD next
Kategorie Clock & Timing RF Modules
Lebenszyklusstatus Aktiv Aktiv
Lagerstatus In Stock In Stock
Stückpreis (USD) $1,28 $10,50
Funktion 1 LVTTL input to 4 LVDS output repeater / fanout buffer —
Datenrate 400 Mbps —
Max Clock Frequency 400 MHz —
Versorgungsspannung 3 V to 3.6 V (typical 3.3 V) [DATA_NEEDED: VBAT operating range]
Input Type LVTTL (single-ended) —
Ausgangstyp LVDS (differential), 4 pairs —
Output Voltage (typical) 350 mV into 100 ohm load —
Standard Compliance ANSI EIA/TIA-644 LVDS —
Kanäle 1 x 1:4 —
Gehäuse 16-TSSOP (PW) —
Montageart Surface Mount Surface Mount (reflow)
Technology LVDS differential signaling —
Kategorie Signal Buffers, Repeaters, Splitters - Clock Buffer —
Betriebstemperatur [DATA_NEEDED: operating temperature range] -40C to +85C
Ruhestrom [DATA_NEEDED: quiescent current] —
Input Rise/Fall Time Note TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance —
Product Type — Sigfox-certified RF transceiver module
Manufacturer — TD next (Telecom Design)
RF Protocol — Sigfox (Ultra-Narrow-Band LPWAN)
Operating Frequency (RC1) — 868 MHz (ETSI Europe)
Operating Frequency (RC2) — 902-928 MHz (US, Australia, Japan)
Tx Power (RC1) — +14 dBm typical
Tx Power (RC2) — +22 dBm maximum
Receiver Sensitivity — [DATA_NEEDED: receiver sensitivity]
Integrated Microcontroller — ARM Cortex-M0+ (STM32 family)
Clock Reference — Integrated TCXO
Host Interface — UART, SPI, I2C, GPIO
Modulation — Ultra-Narrow-Band (UNB), DBPSK uplink
Maximum Payload Size — 12 bytes per uplink message
Form Factor — Surface-mount LGA castellation module
RoHS-Status — Compliant

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