TD1205 vs SN65LVDS105PWR Comparison
Detailed side-by-side comparison of TD1205 by TD next and SN65LVDS105PWR by Texas Instruments. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Texas Instruments
SN65LVDS105PWR - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI
SN65LVDS105PWR ✓ ActiveSpecification Comparison
| Parameter | TD1205 | SN65LVDS105PWR |
|---|---|---|
| Brand | TD next | Texas Instruments |
| Category | RF Modules | Clock & Timing |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.50 | $1.28 |
| Product Type | Sigfox-certified RF transceiver module | — |
| Manufacturer | TD next (Telecom Design) | — |
| RF Protocol | Sigfox (Ultra-Narrow-Band LPWAN) | — |
| Operating Frequency (RC1) | 868 MHz (ETSI Europe) | — |
| Operating Frequency (RC2) | 902-928 MHz (US, Australia, Japan) | — |
| Tx Power (RC1) | +14 dBm typical | — |
| Tx Power (RC2) | +22 dBm maximum | — |
| Receiver Sensitivity | [DATA_NEEDED: receiver sensitivity] | — |
| Integrated Microcontroller | ARM Cortex-M0+ (STM32 family) | — |
| Clock Reference | Integrated TCXO | — |
| Host Interface | UART, SPI, I2C, GPIO | — |
| Modulation | Ultra-Narrow-Band (UNB), DBPSK uplink | — |
| Maximum Payload Size | 12 bytes per uplink message | — |
| Supply Voltage | [DATA_NEEDED: VBAT operating range] | 3 V to 3.6 V (typical 3.3 V) |
| Operating Temperature | -40C to +85C | [DATA_NEEDED: operating temperature range] |
| Form Factor | Surface-mount LGA castellation module | — |
| Mounting Type | Surface Mount (reflow) | Surface Mount |
| RoHS Status | Compliant | — |
| Function | — | 1 LVTTL input to 4 LVDS output repeater / fanout buffer |
| Data Rate | — | 400 Mbps |
| Max Clock Frequency | — | 400 MHz |
| Input Type | — | LVTTL (single-ended) |
| Output Type | — | LVDS (differential), 4 pairs |
| Output Voltage (typical) | — | 350 mV into 100 ohm load |
| Standard Compliance | — | ANSI EIA/TIA-644 LVDS |
| Channels | — | 1 x 1:4 |
| Package | — | 16-TSSOP (PW) |
| Technology | — | LVDS differential signaling |
| Category | — | Signal Buffers, Repeaters, Splitters - Clock Buffer |
| Quiescent Current | — | [DATA_NEEDED: quiescent current] |
| Input Rise/Fall Time Note | — | TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance |