TD1205 vs SN65LVDS105PWR Сравнение
Подробное сравнение бок о бок TD1205 от TD next и SN65LVDS105PWR от Texas Instruments. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Texas Instruments
SN65LVDS105PWR - 1:4 LVDS Clock Fanout Buffer 400Mbps | TI
SN65LVDS105PWR ✓ АктивенСравнение характеристик
| Параметр | TD1205 | SN65LVDS105PWR |
|---|---|---|
| Бренд | TD next | Texas Instruments |
| Категория | RF Modules | Clock & Timing |
| Статус жизненного цикла | Активен | Активен |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $10,50 | $1,28 |
| Product Type | Sigfox-certified RF transceiver module | — |
| Manufacturer | TD next (Telecom Design) | — |
| RF Protocol | Sigfox (Ultra-Narrow-Band LPWAN) | — |
| Operating Frequency (RC1) | 868 MHz (ETSI Europe) | — |
| Operating Frequency (RC2) | 902-928 MHz (US, Australia, Japan) | — |
| Tx Power (RC1) | +14 dBm typical | — |
| Tx Power (RC2) | +22 dBm maximum | — |
| Receiver Sensitivity | [DATA_NEEDED: receiver sensitivity] | — |
| Integrated Microcontroller | ARM Cortex-M0+ (STM32 family) | — |
| Clock Reference | Integrated TCXO | — |
| Host Interface | UART, SPI, I2C, GPIO | — |
| Modulation | Ultra-Narrow-Band (UNB), DBPSK uplink | — |
| Maximum Payload Size | 12 bytes per uplink message | — |
| Напряжение питания | [DATA_NEEDED: VBAT operating range] | 3 V to 3.6 V (typical 3.3 V) |
| Рабочая температура | -40C to +85C | [DATA_NEEDED: operating temperature range] |
| Form Factor | Surface-mount LGA castellation module | — |
| Тип монтажа | Surface Mount (reflow) | Surface Mount |
| Статус RoHS | Compliant | — |
| Функция | — | 1 LVTTL input to 4 LVDS output repeater / fanout buffer |
| Скорость передачи данных | — | 400 Mbps |
| Max Clock Frequency | — | 400 MHz |
| Input Type | — | LVTTL (single-ended) |
| Тип выхода | — | LVDS (differential), 4 pairs |
| Output Voltage (typical) | — | 350 mV into 100 ohm load |
| Standard Compliance | — | ANSI EIA/TIA-644 LVDS |
| Каналы | — | 1 x 1:4 |
| Корпус | — | 16-TSSOP (PW) |
| Technology | — | LVDS differential signaling |
| Категория | — | Signal Buffers, Repeaters, Splitters - Clock Buffer |
| Ток покоя | — | [DATA_NEEDED: quiescent current] |
| Input Rise/Fall Time Note | — | TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance |